An interfacial structure, along with methods of forming such, are described. The structure includes a first interfacial layer having a first dielectric layer, a first conductive feature disposed in the first dielectric layer, and a first thermal conductive layer disposed on the first dielectric layer. The structure further includes a second interfacial layer disposed on the first interfacial layer. The second interfacial layer is a mirror image of the first interfacial layer with respect to an interface between the first interfacial layer and the second interfacial layer. The second interfacial layer includes a second thermal conductive layer disposed on the first thermal conductive layer, a second dielectric layer disposed on the second thermal conductive layer, and a second conductive feature disposed in the second dielectric layer.

A core material has a core; a solder layer provided outside the core and being a solder alloy containing Sn and at least any one element of Ag, Cu, Sb, Ni, Co, Ge, Ga, Fe, Al, In, Cd, Zn, Pb, Au, P, S, Si, Ti, Mg, Pd, and Pt; and a Sn layer provided outside the solder layer. The solder layer has a thickness of 1 μm or more on one side. The Sn layer has a thickness of 0.1 μm or more on one side. A thickness of the Sn layer is 0.215% or more and 36% or less of the thickness of the solder layer.

Disclosed herein is an electronic circuit package includes: a substrate having a power supply pattern; an electronic component mounted on a surface of the substrate; a mold resin covering the surface of the substrate so as to embed therein the electronic component; a magnetic film formed of a composite magnetic material obtained by dispersing magnetic fillers in a thermosetting resin material, the magnetic film covering upper and side surfaces of the molding resin and an edge portion of the front surface exposed to aside surface of the substrate; and a metal film connected to the power supply pattern and covering the molding resin through the magnetic film.

A semiconductor device is proposed. The semiconductor device includes a wiring metal layer structure. The semiconductor device further includes a dielectric layer structure arranged directly on the wiring metal layer structure. The semiconductor device further includes a bonding pad metal layer structure arranged, at least partly, directly on the dielectric layer structure. A layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure. The wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.

A semiconductor device is proposed. The semiconductor device includes a wiring metal layer structure. The semiconductor device further includes a dielectric layer structure arranged directly on the wiring metal layer structure. The semiconductor device further includes a bonding pad metal layer structure arranged, at least partly, directly on the dielectric layer structure. A layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure. The wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.

Disclosed herein is an electronic circuit package includes: a substrate having a power supply pattern; an electronic component mounted on a surface of the substrate; a mold resin covering the surface of the substrate so as to embed therein the electronic component; a laminated structure of a magnetic film and a metal film, the laminated structure covering at least an upper surface of the molding resin. The metal film is connected to the power supply pattern, and a resistance value at an interface between the magnetic film and the metal film is equal to or larger than 10.sup.6Ω.

A mounting structure includes a bonding material (106) that bonds second electrodes (104) of a circuit board (105) and bumps (103) of a semiconductor package (101), the bonding material (106) being surrounded by a first reinforcing resin (107). Moreover, a portion between the outer periphery of the semiconductor package (101) and the circuit board (105) is covered with a second reinforcing resin (108). Even if the bonding material (106) is a solder material having a lower melting point than a conventional bonding material, high drop resistance is obtained.

Dual-side reinforcement (DSR) materials and methods for semiconductor fabrication. The DSR materials exhibit the properties of conventional underfill materials with enhanced stability at room temperature.

Dual-side reinforcement (DSR) materials and methods for semiconductor fabrication. The DSR materials exhibit the properties of conventional underfill materials with enhanced stability at room temperature.

A semiconductor device according to the present invention includes a semiconductor chip, an electrode pad made of a metal material containing aluminum and formed on a top surface of the semiconductor chip, an electrode lead disposed at a periphery of the semiconductor chip, a bonding wire having a linearly-extending main body portion and having a pad bond portion and a lead bond portion formed at respective ends of the main body portion and respectively bonded to the electrode pad and the electrode lead, and a resin package sealing the semiconductor chip, the electrode lead, and the bonding wire, the bonding wire is made of copper, and the entire electrode pad and the entire pad bond portion are integrally covered by a water-impermeable film.