A device is disclosed. The device includes a gate conductor, a first source-drain region and a second source-drain region. The device includes a first air gap space between the first source-drain region and a first side of the gate conductor and a second air gap space between the second source-drain region and a second side of the gate conductor. A hard mask layer that includes holes is under the gate conductor, the first source-drain region, the second source-drain region and the air gap spaces. A planar dielectric layer is under the hard mask.

A device is disclosed. The device includes a gate conductor, a first source-drain region and a second source-drain region. The device includes a first air gap space between the first source-drain region and a first side of the gate conductor and a second air gap space between the second source-drain region and a second side of the gate conductor. A hard mask layer that includes holes is under the gate conductor, the first source-drain region, the second source-drain region and the air gap spaces. A planar dielectric layer is under the hard mask.

The present disclosure provides a method of manufacturing a semiconductor device. The method includes steps of providing a first wafer including a first substrate and a plurality of first conductors over the first substrate; forming a first interconnect structure penetrating through the first substrate and contacting one of the first conductors; forming a bonding dielectric on the first substrate and the first interconnect structure; bonding a second wafer on the first wafer, wherein the second wafer includes a second substrate, a second ILD layer on a second front surface of the second substrate, and a plurality of second conductors in the second ILD layer, wherein the second ILD layer is in contact with the bonding dielectric; forming a second interconnect structure penetrating through the second substrate and into the second ILD layer and contacting the second conductor and the first interconnect structure.

The present disclosure provides a method of manufacturing a semiconductor device. The method includes steps of providing a first wafer including a first substrate and a plurality of first conductors over the first substrate; forming a first interconnect structure penetrating through the first substrate and contacting one of the first conductors; forming a bonding dielectric on the first substrate and the first interconnect structure; bonding a second wafer on the first wafer, wherein the second wafer includes a second substrate, a second ILD layer on a second front surface of the second substrate, and a plurality of second conductors in the second ILD layer, wherein the second ILD layer is in contact with the bonding dielectric; forming a second interconnect structure penetrating through the second substrate and into the second ILD layer and contacting the second conductor and the first interconnect structure.

Three-dimensional memory devices in the form of a memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Bit lines are electrically connected to an end portion of a respective one of the vertical semiconductor channels. Bump connection via structures contact a top surface of a respective one of the bit lines, in which each of the bump connection via structures has a greater lateral dimension along a lengthwise direction of the bit lines than along a widthwise direction of the bit lines. Metallic bump structures of another semiconductor die contact respective ones of the bump connection via structures to make respective electrical connections between the two dies.

Three-dimensional memory devices in the form of a memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Bit lines are electrically connected to an end portion of a respective one of the vertical semiconductor channels. Bump connection via structures contact a top surface of a respective one of the bit lines, in which each of the bump connection via structures has a greater lateral dimension along a lengthwise direction of the bit lines than along a widthwise direction of the bit lines. Metallic bump structures of another semiconductor die contact respective ones of the bump connection via structures to make respective electrical connections between the two dies.

The present disclosure provides a method of manufacturing a semiconductor device. The method includes steps of providing a first wafer including a first substrate and a plurality of first conductors over the first substrate; forming a first interconnect structure penetrating through the first substrate and contacting one of the first conductors; forming a bonding dielectric on the first substrate and the first interconnect structure; bonding a second wafer on the first wafer, wherein the second wafer includes a second substrate, a second ILD layer on a second front surface of the second substrate, and a plurality of second conductors in the second ILD layer, wherein the second ILD layer is in contact with the bonding dielectric; forming a second interconnect structure penetrating through the second substrate and into the second ILD layer and contacting the second conductor and the first interconnect structure.

The present disclosure provides a method of manufacturing a semiconductor device. The method includes steps of providing a first wafer including a first substrate and a plurality of first conductors over the first substrate; forming a first interconnect structure penetrating through the first substrate and contacting one of the first conductors; forming a bonding dielectric on the first substrate and the first interconnect structure; bonding a second wafer on the first wafer, wherein the second wafer includes a second substrate, a second ILD layer on a second front surface of the second substrate, and a plurality of second conductors in the second ILD layer, wherein the second ILD layer is in contact with the bonding dielectric; forming a second interconnect structure penetrating through the second substrate and into the second ILD layer and contacting the second conductor and the first interconnect structure.

Three-dimensional memory devices in the form of a memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Bit lines are electrically connected to an end portion of a respective one of the vertical semiconductor channels. Bump connection via structures contact a top surface of a respective one of the bit lines, in which each of the bump connection via structures has a greater lateral dimension along a lengthwise direction of the bit lines than along a widthwise direction of the bit lines. Metallic bump structures of another semiconductor die contact respective ones of the bump connection via structures to make respective electrical connections between the two dies.

Three-dimensional memory devices in the form of a memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Bit lines are electrically connected to an end portion of a respective one of the vertical semiconductor channels. Bump connection via structures contact a top surface of a respective one of the bit lines, in which each of the bump connection via structures has a greater lateral dimension along a lengthwise direction of the bit lines than along a widthwise direction of the bit lines. Metallic bump structures of another semiconductor die contact respective ones of the bump connection via structures to make respective electrical connections between the two dies.