Structures and methods are disclosed for fabricating optoelectronic solid state array devices. In one case a backplane and array of micro devices is aligned and connected through bumps.

A display device comprises a first electrode, a first insulating layer disposed on the first electrode, a second electrode disposed on the first insulating layer, at least a part of the second electrode facing the first electrode in a first direction, one or more first light-emitting elements disposed between the first electrode and the second electrode, the one or more first light-emitting elements extending in a direction, wherein the first insulating layer partially encompasses the outer surface of the one or more first light-emitting element, and the extending direction of at least one of the one or more first light-emitting element is parallel to the first direction.

A display device comprises a first electrode, a first insulating layer disposed on the first electrode, a second electrode disposed on the first insulating layer, at least a part of the second electrode facing the first electrode in a first direction, one or more first light-emitting elements disposed between the first electrode and the second electrode, the one or more first light-emitting elements extending in a direction, wherein the first insulating layer partially encompasses the outer surface of the one or more first light-emitting element, and the extending direction of at least one of the one or more first light-emitting element is parallel to the first direction.

A package includes a first die, a second die, a first encapsulant, first through insulating vias (TIV), a second encapsulant, and second TIVs. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The first TIVs are aside the first die. The first TIVs penetrate through the first encapsulant and are electrically floating. The second encapsulant laterally encapsulates the second die. The second TIVs are aside the second die. The second TIVs penetrate through the second encapsulant and are electrically floating. The second TIVs are substantially aligned with the first TIVs.

A package includes a first die, a second die, a first encapsulant, first through insulating vias (TIV), a second encapsulant, and second TIVs. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The first TIVs are aside the first die. The first TIVs penetrate through the first encapsulant and are electrically floating. The second encapsulant laterally encapsulates the second die. The second TIVs are aside the second die. The second TIVs penetrate through the second encapsulant and are electrically floating. The second TIVs are substantially aligned with the first TIVs.

An underfill film for semiconductor packages and a method for manufacturing a semiconductor package using the underfill film are disclosed. The underfill film includes an adhesive layer in which a melt viscosity and an onset temperature are adjusted to a predetermined range such that production efficiency may be improved by simplifying packaging process of the semiconductor packages. Also the underfill film and the manufacturing process may improve connection reliability of the package.

An underfill film for semiconductor packages and a method for manufacturing a semiconductor package using the underfill film are disclosed. The underfill film includes an adhesive layer in which a melt viscosity and an onset temperature are adjusted to a predetermined range such that production efficiency may be improved by simplifying packaging process of the semiconductor packages. Also the underfill film and the manufacturing process may improve connection reliability of the package.

A semiconductor package manufacturing method of the disclosure includes providing a multilayer adhesive film, forming a notch and a plurality of openings extending through the multilayer adhesive film, attaching the multilayer adhesive film to a back side of a wafer to form a stack, separating the stack into a plurality of individual stacks, separating each of the plurality of individual stacks into an upper stack and a lower stack, providing a substrate on which a first semiconductor chip is mounted, and stacking the upper stack on the first semiconductor chip. The upper stack includes a second semiconductor chip and a die attach pattern covering a portion of a back surface of the second semiconductor chip. A first side surface of the die attach pattern is aligned with a first side surface of the first semiconductor chip.

A semiconductor package manufacturing method of the disclosure includes providing a multilayer adhesive film, forming a notch and a plurality of openings extending through the multilayer adhesive film, attaching the multilayer adhesive film to a back side of a wafer to form a stack, separating the stack into a plurality of individual stacks, separating each of the plurality of individual stacks into an upper stack and a lower stack, providing a substrate on which a first semiconductor chip is mounted, and stacking the upper stack on the first semiconductor chip. The upper stack includes a second semiconductor chip and a die attach pattern covering a portion of a back surface of the second semiconductor chip. A first side surface of the die attach pattern is aligned with a first side surface of the first semiconductor chip.

A package includes a first die, a second die, an encapsulant, and a redistribution structure. The first die has a first capacitor embedded therein. The second die has a second capacitor embedded therein. The second die is stacked on the first die. The first capacitor is electrically connected to the second capacitor. The encapsulant laterally encapsulates the second die. The redistribution structure is disposed on the second die and the encapsulant.