A semiconductor device includes a substrate, an insulating layer on a bottom surface of the substrate, a portion of a top surface of the insulating layer that faces the substrate being exposed outside a side surface of the substrate, a through via penetrating the substrate, an interconnection structure in the insulating layer, and a dummy pattern on the portion of the top surface of the insulating layer that is exposed by the substrate.

The invention relates to a switch system comprising one or more optical transceiver assemblies (14) connected to a switch ASIC (29).

A semiconductor package includes a plurality of first semiconductor structures that are stacked on a package substrate and are offset from each other in a first direction, and a plurality of first adhesive layers disposed between the first semiconductor structures. Each of the first semiconductor structures includes a first sub-chip and a second sub-chip in contact with a part of a top surface of the first sub-chip. The first adhesive layers are disposed between and are in contact with the first sub-chips. The first adhesive layers are spaced apart from the second sub-chips. A thickness of each of the first adhesive layers is less than a thickness of each of the second sub-chips. The thickness of the second sub-chip is in a range of about 13 μm to about 20 μm.

A device assembly includes a functional substrate having one or more electronic components formed there. The functional substrate has a cavity extending from a first surface toward a second surface of the functional substrate at a location that lacks the electronic components. The device assembly further includes a semiconductor die placed within the cavity with a pad surface of the semiconductor die being opposite to a bottom of the cavity. The functional substrate may be formed utilizing a first fabrication technology and the semiconductor die may be formed utilizing a second fabrication technology that differs from the first fabrication technology.

A device assembly includes a functional substrate having one or more electronic components formed there. The functional substrate has a cavity extending from a first surface toward a second surface of the functional substrate at a location that lacks the electronic components. The device assembly further includes a semiconductor die placed within the cavity with a pad surface of the semiconductor die being opposite to a bottom of the cavity. The functional substrate may be formed utilizing a first fabrication technology and the semiconductor die may be formed utilizing a second fabrication technology that differs from the first fabrication technology.

The invention relates to a thermode for connecting at least two components, comprising a tip having a body portion with at least two contact surface portions connected to and spaced apart from one another by a recess configured to receive a portion of one of the at least two components; and a support portion having at least one supporting surface portion configured to support a further component (being the other of the at least two components, wherein the contact surface portions and the supporting surface portion are configured to receive the at least two components between them and wherein one or both of the contact surface portions and the supporting surface portion are moveable relative to and towards one another to exert heat and/or pressure on the at least two components located between the contact surface portions and the supporting portion.

Some embodiments include an integrated assembly having a conductive line supported by a deck and extending along a longitudinal direction. The conductive line is configured to carry an electrical signal. A connection region is along the conductive line. The conductive line splits amongst multiple components as it passes through the connection region. The components are spread-apart from one another along a lateral direction which is orthogonal to the longitudinal direction. An opening extends vertically through the deck and through the connection region. The opening breaks one of the components of the conductive line to leave another of the components to carry the electrical signal across the connection region.

Techniques of minimizing or eliminating stresses in silicon photonic integrated circuits (Si-PICs) and in semiconductor packages having one or more Si-PICs (Si-PIC packages) are described. An Si-PIC or an Si-PIC package includes a stress minimization solution that assists with filtering out stresses by selectively isolating photonic and/or electronic devices, by isolating components or devices in an Si-PIC or an Si-PIC package that are sources of stress, or by isolating an Si-PIC in an Si-PIC package. The stress minimization solution may include strategically placed cavities and a stage that assist with minimizing or preventing transfer of stress to one or more photonic and/or electronic devices in an Si-PIC or an Si-PIC package.

Some embodiments include an integrated assembly having a conductive line supported by a deck and extending along a longitudinal direction. The conductive line is configured to carry an electrical signal. A connection region is along the conductive line. The conductive line splits amongst multiple components as it passes through the connection region. The components are spread-apart from one another along a lateral direction which is orthogonal to the longitudinal direction. An opening extends vertically through the deck and through the connection region. The opening breaks one of the components of the conductive line to leave another of the components to carry the electrical signal across the connection region.

Described herein are semiconductor devices and structures with improved power handling and heat dissipation. Embodiments are suitable for implementation in gallium nitride. Devices may be provided as individual square or diamond-shaped dies having electrode terminals at the die corners, tapered electrode bases, and interdigitated electrode fingers. Device matrix structures include a plurality of device dies arranged on a substrate in a matrix configuration with interdigitated conductors. Device lattice structures are based on a unit cell comprising a plurality of individual devices, the unit cells disposed on a chip with geometric periodicity. Also described herein are methods for implementing the semiconductor devices and structures.