A method for bonding chips includes actuating a first bonding head to apply a first force to a first chip while the first chip is contacting a bonding surface, thereby partially bonding the first chip to the bonding surface, actuating a second bonding head to apply a second force to a second chip while the second chip is contacting the bonding surface, thereby partially bonding the second chip to the bonding surface, and collectively actuating the first bonding head and the second bonding head to apply a third force to the first chip and the second chip such that the first chip and the second chip are completely bonded to the bonding surface. A magnitude of the third force is larger than a magnitude of the first force and a magnitude of the second force.

Disclosed herein is a package comprising a first die having a first redistribution layer (RDL) disposed on a first side of a first substrate and a second die having a second RDL disposed on a first side of a second substrate, with the first RDL bonded to the second RDL. A third die having a third RDL is disposed on a first side of a third substrate, the third die mounted over the second die, with the second die disposed between the first die and the third die. First vias extend through, and are electrically isolated from, the second substrate, with the first vias each contacting a conductive element in the first RDL or the second RDL. Second vias extend through, and are electrically isolated from, the third substrate, with the second vias each contacting a conductive element in the third RDL or one of the first vias.

A semiconductor device and a method of making the same. The device includes a semiconductor substrate having a major surface, a backside and side surfaces extending between the major surface and the backside. The semiconductor device also includes at least one metal layer extending across the backside of the substrate. A peripheral part of the at least one metal layer located at the edge of the substrate between the backside and at least one of the side surfaces extends towards a plane containing the major surface. This can prevent burrs located at the peripheral part of the at least one metal layer interfering with the mounting of the backside of the substrate on the surface of a carrier.

The present disclosure relates to silver paste, and a preparation method and a use thereof, which belong to the field of device packaging technology. The silver paste of the present disclosure is prepared by a silver-ammonia complex and an aldehyde-containing organic solvent, wherein a molar ratio of the silver-ammonia complex to the aldehyde-containing organic solvent is in a range of from 1:1 to 1:5; the silver-ammonia complex is prepared by a silver -ketocarboxylate and an amino-containing organic solvent; and a molar ratio of the silver -ketocarboxylate to the amino-containing organic solvent is in a range of from 1:1 to 1:5. The silver paste of the present disclosure can achieve large-area (3030 cm.sup.2) packaging and interconnection of a wide-bandgap semiconductor device within 300 C. under a low pressure (1 MPa) or without pressures.

A fan-out package structure and a fan-out package method are provided. The fan-out package structure includes: a chip, an inner substrate, a bonding patch layer, an encapsulation layer, an insulation support layer, an interconnection line structure, package pins, a first electrically conductive layer and a second electrically conductive layer.

A method for the connection of electronic components, in which (a) a sandwich arrangement is provided, which comprises at least (a1) an electronic component 1, (a2) an electronic component 2, and (a3) a metal sintering preparation being situated between metal contact surfaces of the electronic components 1 and 2, and in which (b) the sandwich arrangement is being pressureless sintered, wherein the method takes place in an ambient gas atmosphere, and wherein an exchange of the ambient gas atmosphere is made within the course of the pressureless metal sintering process.

A substrate bonding method includes a plasma processing step of processing a bonding surface of each of the substrates with a rare gas plasma which is a plasma of a rare gas, processing the bonding surface of each of the substrates processed with the rare gas plasma with a hydrogen plasma which is a plasma of hydrogen, and processing the bonding surface of each of the substrates processed with the hydrogen plasma with a nitrogen plasma which is a plasma of nitrogen and a substrate bonding step of bonding two substrates by bringing the bonding surfaces of the two substrates into contact with each other such that copper pads of the two substrates face each other and insulating films of the two substrates face each other after the plasma processing step.

It is possible to suppress occurrence of a void when filling underfill material between a substrate and a semiconductor chip. There is provided a technique that includes: performing at least one among: (a) forming an insulating film on a first surface of a substrate and a first microbump formed on the first surface, wherein the first surface faces a semiconductor chip when the substrate and the semiconductor chip are bonded together; and (b) forming the insulating film on a second surface of the semiconductor chip and a second microbump formed on the second surface, wherein the second surface faces the substrate when the substrate and the semiconductor chip are bonded together.