SEMICONDUCTOR DEVICE AND METHOD OF MAKING A SEMICONDUCTOR DEVICE

Abstract

A semiconductor device and a method of making the same. The device includes a semiconductor substrate having a major surface, a backside and side surfaces extending between the major surface and the backside. The semiconductor device also includes at least one metal layer extending across the backside of the substrate. A peripheral part of the at least one metal layer located at the edge of the substrate between the backside and at least one of the side surfaces extends towards a plane containing the major surface. This can prevent burrs located at the peripheral part of the at least one metal layer interfering with the mounting of the backside of the substrate on the surface of a carrier.

Claims

1. A semiconductor device comprising: a semiconductor substrate having a major surface, a backside and side surfaces extending between the major surface and the backside; and at least one metal layer extending across the backside of the substrate, wherein a peripheral part of the at least one metal layer located at the edge of the substrate between the backside and at least one of the side surfaces extends towards a plane containing the major surface, to prevent burrs located at the peripheral part of the at least one metal layer interfering with the mounting of the backside of the substrate on the surface of a carrier.

2. The semiconductor device of claim 1, wherein an edge of the substrate between the backside and at least one of the side surfaces is curved, and wherein the peripheral part of the at least one metal layer extends along the curved edge of the substrate.

3. The semiconductor device of claim 1, wherein an edge of the substrate between the backside and at least one of the side surfaces slants upwards at an angle 180>>90 relative to a surface normal of the backside, and wherein the peripheral part of the at least one metal layer extends along the slanted edge of the substrate.

4. The semiconductor device of claim 1, wherein an edge of the substrate between the backside and at least one of the side surfaces includes a substantially L-shaped step portion having a corner pointing inwards towards a bulk region of the substrate, and wherein the peripheral part of the at least one metal layer extends along the substantially L-shaped step portion.

5. The semiconductor device of claim 1, wherein an edge of the substrate between the backside and at least one of the side surfaces includes a protrusion that extends outwardly from the side surface and that has a surface that extends upwardly towards the plane containing the major surface, and wherein the peripheral part of the at least one metal layer extends along the surface that extends upwardly towards the plane containing the major surface.

6. The semiconductor device of claim 1, wherein the substrate comprises one or more active components located at the major surface.

7. The semiconductor device of claim 1, wherein the at least one metal layer comprises a stack of metal layers located on the backside of the substrate.

8. A wafer level chip scale package comprising the semiconductor device of claim 1.

9. A method of making a semiconductor device, the method comprising: providing a semiconductor wafer having a major surface and a backside; forming an array of trenches in the backside of the substrate; depositing at least one metal layer on the backside of the wafer, wherein the at least one metal layer extends across the backside of the wafer and coats an inner surface of the trenches; and singulating the wafer substantially along lines defined by the trenches, wherein said singulation produces a plurality of semiconductor devices, each device comprising: a semiconductor substrate having a major surface corresponding to the major surface of the wafer, a backside corresponding to the backside of the wafer and side surfaces extending between the major surface of the substrate and the backside of the substrate; and at least one metal layer extending across the backside of the substrate, wherein a peripheral part of the at least one metal layer located at the edge of e each substrate between the backside and at least one of the side surfaces extends towards a plane containing the major surface of the substrate, to prevent burrs located at the peripheral part of the at least one metal layer interfering with the mounting of the backside of the substrate on the surface of a carrier, and wherein the peripheral part of the at least one metal layer of each substrate corresponds to a part of the at least one metal layer on the backside of the wafer coating the an inner surface of the trenches.

10. method of claim 9, wherein at least some of the trenches have rounded corners.

11. The method of claim 9, wherein at least some of the trenches are substantially V-shaped.

12. The method of claim 9, wherein at least some of the trenches are substantially rectangular.

13. The method of claim 1, wherein singulating the wafer comprises sawing the wafer from the major surface of the wafer downwards until the sawing meets the array of trenches in the backside of the substrate.

14. The method of claim 9, wherein singulating the wafer substantially along lines defined by the trenches comprises sawing the wafer using saw lanes having a width that is smaller than a lateral width of the trenches.

15. The method of claim 9, comprising mounting the backside of the substrate of at least some of the semiconductor devices on the surface of a carrier.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Embodiments of this disclosure will be described hereinafter, by way of example only, with reference to the accompanying drawings in which like reference signs relate to like elements and in which:

[0037] FIGS. 1A to 1C show a process for singulating a semiconductor wafer to produce a plurality of semiconductor devices;

[0038] FIG. 2 shows one of the semiconductor devices produced by the example of FIG. 1 mounted on a lead frame;

[0039] FIGS. 3A to 3D show a process for singulating a semiconductor wafer to produce a plurality of semiconductor devices according to an embodiment of this disclosure;

[0040] FIG. 4 shows one of the semiconductor devices produced by the process of FIGS. 3A to 3D mounted on a carrier;

[0041] FIGS. 5A to 5D show other examples of the singulation of a semiconductor wafer according to an embodiment of this disclosure;

[0042] FIGS. 6A to 6D show a process for singulating a semiconductor wafer to produce a plurality of semiconductor devices according to a further embodiment of this disclosure.

DETAILED DESCRIPTION

[0043] Embodiments of this disclosure are described in the following with reference to the accompanying drawings.

[0044] FIGS. 1A to 1C show a process for singulating a semiconductor wafer to produce a plurality of semiconductor devices. In FIG. 1A, there is provided a semiconductor wafer 10. The wafer has a plurality of active regions 4 located on a major surface of the wafer 10. As shown in FIG. 1B, a backside of the wafer, which is the surface of the wafer 10 opposite the major surface, may be provided with at least one metal layer 16. Backside metallisation is well known in the field of semiconductor device manufacture and will not be described here in detail.

[0045] Next, as shown in FIG. 1C, the wafer 10 is placed on a dicing tape 20. The dicing tape supports the wafer during singulation. FIG. 1C also shows the singulation of the wafer along saw lanes 70 to produce a number of semiconductor devices comprising separate substrates. Since the metal of the at least one metal layer 16 may be ductile, the sawing can produce burrs 8 at the edges of the substrates. This may be exacerbated by the fact that the saw lanes 70 may extend at least partially into the dicing tape 20.

[0046] FIG. 2 shows one of the semiconductor devices produced by the example of FIG. 1 mounted on a lead frame 10. The device includes a substrate 2 having at least one metal layer 6 located on the backside thereof. As can be seen in FIG. 2, the burrs 8 hanging down beneath the substrate 2 can inhibit correct mounting of the substrate 2 on the lead frame 10. For instance, the burrs 8 can prevent the least one metal layer 6 from sitting flush against the surface of the lead frame 10. A void 12 can arise between the surface of the carrier and the at least one metal layer 6. This can prevent correct mechanical, thermal and/or electrical contact being formed between the at least one metal layer 6 and the lead frame 10. As described previously, any solder that is used to mount the substrate 2 on the lead frame 10 may also short with the edges of some of the metal layers of the at least one metal layer 6 that have been exposed by the sawing.

[0047] Embodiments of this disclosure can provide a semiconductor device in which any burrs that are formed at a peripheral part of at least one metal layer provided on the backside of a substrate need not necessarily interfere with the mounting of the backside of the substrate on the surface of a carrier. This may be achieved by shaping the peripheral part of the at least one metal layer located at the edge of the substrate between a backside of the substrate and at least one of the side surfaces of the substrate extends towards a plane containing a major surface of the substrate. This shaping of the peripheral part of the at least one metal layer may physically separate any burrs located at the peripheral part of the at least one metal layer from the backside of the substrate, so that they do not hang down beneath the substrate. The shaping of the peripheral part of the substrate in this way may also prevent shorting of the exposed edges of some of the at least one metal later with solder that may be used to mount the substrate on a carrier.

[0048] FIGS. 3A to 3D show a process for making a semiconductor device according to an embodiment of this disclosure. In a first step, shown in FIG. 3A, there is provided a semiconductor wafer 40. The wafer 40 may, for instance, comprise a silicon wafer, although other kinds of wafer are also envisaged (e.g. the wafer may comprise GaN).

[0049] The wafer 40 has a major surface 22 and a backside 24. The backside 24 is a surface of the wafer 40 opposite the major surface 22. The wafer may be processed using conventional manufacturing techniques to form active regions 34 on the major surface 22. These active regions 34 may include active components such as transistors, diodes, sensors etc. Passive components such as capacitors, inductors and metal tracks connecting together the various components of the active regions 34 may also be provided. The major surface 22 may also be provided with one or more electrical contacts for connecting to the components of the active regions 34.

[0050] In a next step, shown in FIG. 3B, an array of trenches 60 is formed in the backside of the substrate. The trenches 60 may, for instance, be formed by partial sawing of the backside 24. In other examples, lithographic techniques may be used to mask and wet etch the backside to form the array. In a further example, plasma etching may be used. The array of trenches 60 may have a layout corresponding to the saw lanes that will subsequently be used to singulate the wafer 40. Accordingly, the array of trenches may delineate the plurality of semiconductor substrates that will subsequently be produced by singulating the wafer 40. The array of trenches 60 may be a regular, repetitive array. The array of trenches 60 may, for instance, be a rectangular array (e.g. the substrates to be produced by subsequent singulation of the wafer 40 may be square or oblong).

[0051] In a next step, shown in FIG. 3B, at least one metal layer 36 may be deposited on the backside 24 of the wafer 40.

[0052] In some examples, there may only be a single metal layer on the backside 24. In other examples, the at least one metal layer 36 may be provided as a stack comprising a plurality of metal layers. An outermost metal layer of the stack can be used to mount the semiconductor device described herein to the surface of a carrier, and the metal used for this outermost layer may be chosen to be compatible with the solder. On the other hand, other metal layers located inside the stack may comprise a metal that may have an adverse chemical reaction with the solder, were that layer to come into contact with the solder. In accordance with embodiments of this disclosure, since a peripheral part of the metal layers in the stack may extend towards a plane containing the major surface, any solder that may be used to mount the backside of the substrate on the surface of the carrier may not come into contact with, and have an adverse chemical reaction with, the edges of one or more of the metal layers inside the stack.

[0053] The metal of the at least one metal layer 36 may, for instance, comprise metals such as Cu, Sn. Note that the metal layers may comprise a metal alloy. Where the at least one metal layer is provided as a stack as described herein, the stack may, for instance, include a layer of Cu and a layer of Sn. In such examples, a Cu metal layer in the stack may have an adverse chemical reaction if it comes into contact with solder. As already mentioned above, this problem may be avoided in accordance with embodiments of this disclosure, since a peripheral part of the metal layers in the stack may extend towards a plane containing the major surface. Further examples include Titanium-Gold-Nickel, Gold-Arsenic or Gold-Germanium, or even pure Silver or Gold on the backside.

[0054] As shown in FIG. 3C, the at least one metal layer 36 extends across the backside 24 of the wafer 40. FIG. 3C also shows that the at least one metal layer 36 also coats an inner surface of the trenches of the array of trenches 60.

[0055] In a next step, shown in FIG. 3D, the wafer 40 is singulated along saw lanes 70 to produce a plurality of semiconductor devices each comprising a respective one of the singulated substrates. In the present example, the saw lanes 70 correspond exactly in position to the layout of the array of trenches 60. As will be described in more detail below in relation to FIGS. 5A to 5D, singulating the wafer 40 along the trenches 60 need not involve aligning the saw lanes 70 precisely with the trenches 60there may be a degree of tolerance involved. Also, in the present example, the saw lanes 70 are roughly equal in width to the trenches of the array of trenches 60 formed in FIG. 3B. However, as will be described in more detail below in relation to FIGS. 5B, 5C, 5D, 6C and 6D, the saw lanes 70 may be narrower than the trenches of the array of trenches 60.

[0056] The sawing of the wafer 40 may begin at the major surface 22 and continue until the sawing reaches to tops of the trenches of the array of trenches 60, at which point the substrates become separated. It may not be necessary for the sawing to continue further down than this point. Indeed, continued sawing of this kind may produce unwanted burrs to be produced, notwithstanding the measured described herein. On the other hand, as described below in relation to FIG. 6, if the saw lanes 70 are narrower than the trenches of the array of trenches 60, this problem may not arise.

[0057] FIG. 4 shows one of the semiconductor devices produced by the process of FIGS. 3A to 3D mounted on a carrier 10. The carrier 10 may, for instance, be a lead frame, heat sink or flange. In a further example, the carrier 10 may be a substrate with, for example, a Cu insert for better thermal behavior.

[0058] The device includes a semiconductor substrate 32 having a major surface that corresponds to the major surface 22 of the wafer 40 and a backside that corresponds to the backside 24 of the wafer 40. The semiconductor substrate 32 also includes a number of side surfaces 35 (typically there are four such surfaces, in the case of a rectangular substrate).

[0059] The major surface of the substrate 32 may include an active region 34 of the kind described above, including one or more active and passive components and one or more electrical contacts.

[0060] The device also includes at least one metal layer 36 extending across the backside of the substrate 32, which corresponds to the at least one metal layer 36 described above in relation to FIG. 3C.

[0061] As shown in FIG. 4, the at least one metal layer 36 has a peripheral part 38. The peripheral part 38 is located at the edges of the substrate 32, which edges are the edges between the backside and the side surfaces 35 of the substrate. These edges may be configured and shaped in an number of different ways, as described below.

[0062] The peripheral part 38 of the at least one metal layer 36 extends towards the plane containing the major surface of the substrate 32. The plane containing the major surface of the substrate 32 is indicated by the dashed line labelled 200 in FIG. 4. In the present example, the peripheral part 38 extends upwards along one or more of the side surfaces 35 of the substrate 32, although other configurations are envisaged, as will be described below. Note that the peripheral part 38 corresponds to a part of the metal coating an inner surface of the array of trenches 60 as described above in relation to FIG. 3C. The effect of shaping the peripheral part 38 of the at least one metal layer 36 in this way is that the at least one metal layer 36 terminates at a location that is physically separated from the back of the substrate 32. Accordingly, any burrs located at the peripheral part 38 of the at least one metal layer tend also to be physically separated from the backside of the substrate 32. Thus, any such burrs, even burrs hanging directly downwards, would tend not to interfere with the mounting of the backside of the substrate 32 on the surface of a carrier 10. As can be seen in FIG. 4, the backside of the substrate 32 sits flush against the surface of the carrier, without there being any void between the substrate 32 and the carrier 10 of the kind described above in relation to FIG. 2.

[0063] It is also envisaged that, in cases where the at least one metal layer 36 comprises a plurality of metal layers in a stack, the shaping of the peripheral part 38 in this way may prevent solder unintentionally coming into contact with, and having an adverse chemical reaction with, the edges of any metal layers located inside the stack. This is because the edges of these layers inside the stack may terminate at a location that is physically removed from the location of the solder.

[0064] FIG. 5A shows a one of the saw lanes 70 between two singulated semiconductor substrates 32A, 32B in more detail. As with FIG. 3D, the saw lane 70 in this example is roughly the same width as the trenches of the array of trenches 60 formed in the backside 24 of the wafer 40 prior to singulation. However, in this example, although the wafer 40 has been singulated along the array of trenches 60, the saw lane 70 is not precisely aligned with the trenches.

[0065] FIG. 5A demonstrates that there is a degree of tolerance involved in the alignment of the saw lanes 70 with respect to the location of the trenches. Both substrates 32A, 32B include at least one metal layer 36 having a peripheral part 38 that extends towards a plane containing the major surface of that substrate 32A, 32B, and this can prevent burrs located at the peripheral part 38 interfering with the mounting of the backside of the substrate 32A, 32B on the surface of a carrier. However, as a consequence of the slight misalignment between the saw lane 70 and the trench, the edges of the substrate 32A between the backside of the substrate 32A the side surface 35A are shaped differently to the edges of the substrate 32B between the backside of the substrate 32B the side surface 35B.

[0066] An edge of the substrate 32A between the backside of the substrate 32A and the side surface 35A includes a protrusion 42 that extends outwardly from the side surface 35A. The protrusion 42 has a surface 44 that extends upwardly (e.g. substantially parallel to the side surface 35A) towards the plane containing the major surface of the substrate 32A. In this example, the peripheral part 38 of the at least one metal layer 36 extends along the surface 44 and thus itself extends upwardly towards the plane containing the major surface.

[0067] On the other hand, an edge of the substrate 32B between the backside of the substrate 32B and the side surface 35B includes a substantially L-shaped step portion 45 having a corner 46 that points inwards towards a bulk region of the substrate 32B. In this example, the peripheral part 38 of the at least one metal layer 36 extends along the substantially L-shaped step portion, at least as far as the corner 46.

[0068] It will be appreciated that any given substrate 32 produced by the method described herein may include edges between the backside of the substrate 32 side surfaces 35 of the substrate that are shaped and configured in a number of different ways. For instance, it will be appreciated that the substrates 32A, 32B shown in FIG. 5A may each include some edges that include a protrusion 42 and some edges that include a substantially L-shaped step portion 45, depending on the local alignment of the saw lanes 70.

[0069] While FIG. 5A demonstrates that there is a degree of tolerance involved in the alignment of the saw lanes 70 with respect to the location of the trenches 60, in the context of a saw lane that is of comparable width to the trenches 60, FIGS. 5B to 5D demonstrate that this is also true in the context of saw lanes 70 that are narrower than the trenches 60.

[0070] For instance, in FIG. 5B, the saw lane 70, which is narrower than the trench on the backside of the wafer, is well aligned with the trench. Here, the peripheral part 38 of the at least one metal layer 36 extends towards a plane containing the major surface, as noted previously.

[0071] In the example of FIG. 5C, there is some misalignment between the saw lane 70 and the trench on the backside of the wafer. Nevertheless, each of the substrates 32A, 32B still includes a peripheral part 38 of the at least one metal layer 36 extends towards a plane containing the major surface, as noted previously.

[0072] In the example of FIG. 5D, there is a larger misalignment between the saw lane 70 and the trench on the backside of the wafer than shown in FIG. 5C. Nevertheless, each of the substrates 32A, 32B still includes a peripheral part 38 of the at least one metal layer 36 extends towards a plane containing the major surface, as noted previously.

[0073] FIGS. 6A to 6D show another example of a method of making a semiconductor device according to an embodiment of this disclosure.

[0074] Firstly, in FIG. 6A, there is provided a semiconductor wafer 40, which, as noted above may be a silicon wafer or some other kind of wafer. The major surface of the wafer 40 may include active regions 34 of the kind already described.

[0075] As shown in FIG. 6A, an array of trenches is formed in the backside of the wafer 40. The trenches described herein may have a depth of around 20 m, although this would depend upon factors such as the overall thickness of the wafer, the thickness of the trenches and the thickness of the saw lanes produced by subsequent singulation.

[0076] The trenches may be formed by using, for instance, a saw blade 90 having a bevelled tip. The bevelled tip can produce trenches 80 that are substantially V-shaped. When the wafer 40 is subsequently singulated along the trenches, this can produce semiconductor substrates having an edge between the backside of the substrate and at least one of the side surfaces of the substrate that slants upwards at an angle 180>>90 relative to a surface normal of the backside of the substrate. In such examples, peripheral part 38 of the at least one metal layer 36 on the backside of the substrate can extend along the slanted edge of the substrate, thereby to extend towards the plane containing the major surface of the substrate, to prevent any burrs located at the peripheral part 38 interfering with the mounting of the backside of the substrate on the surface of a carrier.

[0077] In another example, as also shown in FIG. 6A, a laser 92 may be used to form trenches 82 having a curved profile. Trenches of this kind can also be used to ensure that, after singulation, the peripheral part 38 of the at least one metal layer 36 on the backside of the substrate extends towards the plane containing the major surface of the substrate.

[0078] In FIG. 6B, an optional step for rounding off the corners of the trenches may be performed. This step may include using an etchant 94 to etch away the sharp corners of the trenches, to produced trenches 84 having a rounded profile. Note that this etching step may be applied to trenches formed by any of the methods described above in relation to FIGS. 3B and 6A. Rounding off of the sharp corners of the trenches in this way may reduce flaking and delamination of the peripheral part of the at least on metal layer on each semiconductor substrate after singulation.

[0079] Following the optional etching step described above, at least one metal layer 36 may be deposited on the backside of the wafer 40 as already described above in relation to FIG. 3C. The at least one metal layer 36 extends across the backside of the wafer 40 and coats an inner surface of the trenches. As already noted, in some examples, the at least one metal layer 36 may comprise a stack including a plurality of metal layers located on the backside of the wafer 40.

[0080] The wafer 40 may then be placed on a dicing tape 50 as shown in FIG. 6C. In particular, the wafer 40 may be placed on the dicing tape 50 with the backside facing downwards against the surface of the dicing tape 50.

[0081] Next, the wafer 40 may be singulated, as also illustrated in FIG. 6C. The singulation of the wafer may be achieved using a saw blade 96 or by any other suitable method (e.g. by laser sawing). The wafer 40 is singulated substantially along lines defined by the trenches, as already discussed. In the present example, the saw lanes 70 (see FIG. 6D) are narrower than the trenches. In such examples, it may not be necessary for the sawing to stop at the point at which the saw lanes meet the tops of the trenches. Due to the relative narrowness of the saw lanes, even in the sawing continues down into dicing tape 50 (as shown in FIG. 6D), any burrs formed by the sawing would still tend to be located away from the backside of each singulated substrate.

[0082] FIG. 6D also shows one of the substrates 32 formed by the method described above mounted on the surface of a carrier 10 such as a lead frame. Note that in this example, the edges of the substrate 32 between the backside and the side surfaces 35 are curved. Note also that the peripheral part 38 of the at least one metal layer 36 extends along the curved edge of the substrate, and thus extends towards a plane containing the major surface of the substrate 32.

[0083] FIG. 6D further shows a burr 100 located at the peripheral part 38 of the at least one metal layer 36 and illustrates that, because the peripheral part 38 extends towards a plane containing the major surface of the substrate 32, the burr 100 is physically separated from the backside of the substrate 32 and does not interfere with the mounting of the substrate 32 on the carrier 10.

[0084] Also shown in FIG. 6D is a portion of solder 110 that is used, in this example, to mount the substrate 32 on the surface of the carrier 10. Note that because the peripheral part 38 extends towards a plane containing the major surface of the substrate 32, the edges of any metal layer(s) of the at least one metal layer 36 are physically separated from the solder 110. For instance, this can prevent the solder 110 coming into contact with, and potentially having an adverse chemical reaction with, any exposed edges of metal layers located within the stack located on the backside of the substrate 32.

[0085] In some embodiments, the semiconductor device described herein may be a wafer level chip scale package (WLCSP).

[0086] Accordingly, there has been described a semiconductor device and a method of making the same. The device includes a semiconductor substrate having a major surface, a backside and side surfaces extending between the major surface and the backside. The semiconductor device also includes at least one metal layer extending across the backside of the substrate. A peripheral part of the at least one metal layer located at the edge of the substrate between the backside and at least one of the side surfaces extends towards a plane containing the major surface. This can prevent burrs located at the peripheral part of the at least one metal layer interfering with the mounting of the backside of the substrate on the surface of a carrier.

[0087] Although particular embodiments of this disclosure have been described, it will be appreciated that many modifications/additions and/or substitutions may be made within the scope of the claims.