Methods for manufacturing an energy storage device. Such methods comprise providing a first stack on a first side of a substrate and a second stack on a second side of the substrate, opposite to the first side of the substrate. In examples, a first and third groove are formed in the first stack, with different depths than each other, and a second and fourth groove are formed in the second stack, with different depths than each other. In other examples, a first groove is formed in the first stack and a second groove is formed in the second stack, in substantial alignment with the first groove but with a different depth than the first groove.

A method for manufacturing an energy storage device. A stack is provided on a substrate. The stack comprises a first electrode layer, a second electrode layer, and an electrolyte layer between the first electrode layer and the second electrode layer. The method includes forming a first groove, a second groove, and a third groove in a first side of the stack opposite to a second side of the stack on the substrate. The first groove has a first depth and a first surface comprising a first exposed surface of the second electrode layer. The second groove has a second depth different from the first depth and a second surface comprising an exposed surface of the first electrode layer. The third groove has a third depth substantially the same as the first depth and a third surface comprising a second exposed surface of the second electrode layer.

A method comprising providing a first electrode layer on a first portion of a substrate, providing an electrolyte layer on the first electrode layer, and providing a second electrode layer on the electrolyte layer. At least part of a current collector layer is provided on a second portion of the substrate. An electrically insulating material is deposited on an exposed surface of the first electrode layer and an exposed surface of the electrolyte layer. An electrically conductive material is deposited on the electrically insulating material to connect the second electrode layer to the at least part of the current collector layer.

A power source for a micro-device is provided. The power source may include a cup, a lid and electrolytes. The cup may be formed of a hard metal material and walls of the cup may define a cavity. An opening in the cup may provide access to the cavity and a surface of the cavity may be deposited with one of an anode or cathode material. The lid may be formed of a hard metal material, the lid may cooperate with the cup to fit into the opening closing off the cavity. The cavity may be coated with the other of the anode or cathode material. Electrolytes may be contained in the cavity;

A semiconductor structure is provided that contains a non-volatile battery which controls gate bias. The non-volatile battery has a stable voltage and thus the structure may be used in neuromorphic computing. The semiconductor structure may include a semiconductor substrate including at least one channel region that is positioned between source/drain regions. A gate dielectric material is located on the channel region of the semiconductor substrate. A battery stack is located on the gate dielectric material. In accordance with the present application, the battery stack includes, an anode current collector located on the gate dielectric material, an anode region located on the anode current collector, an ion diffusion barrier material located on the anode region, an electrolyte located on the ion diffusion barrier material, a cathode material located on the electrolyte, and a cathode current collector located on the cathode material.

The present disclosure provides an embodiment of an integrated structure that includes a first electrode of a first conductive material embedded in a first semiconductor substrate; a second electrode of a second conductive material embedded in a second semiconductor substrate; and a electrolyte disposed between the first and second electrodes. The first and second semiconductor substrates are bonded together through bonding pads such that the first and second electrodes are enclosed between the first and second semiconductor substrates. The second conductive material is different from the first conductive material.

Microbatteries and methods for forming microbatteries are provided. The microbatteries and methods address at least one or both of edge sealing issues for edges of a stack forming part of a microbatteries and overall sealing for individual cells for microbatteries in a batch process. A transferable solder molding apparatus and sealing structure are proposed in an example to provide a metal casing for a solid-state thin-film microbattery. An exemplary proposed process involves deposition or pre-forming low-temperature solder casing separately from the microbatteries. Then a thermal compression may be used to transfer the solder casing to each battery cell, with a handler apparatus in a batch process in an example. These exemplary embodiments can address the temperature tolerance constrain for solid state thin film battery during handling, metal sealing, and packaging.

A three dimensional (3D) In-Silicon energy storage device is provided by a method that includes forming a thick dielectric material layer on a surface of a silicon based substrate. A 3D trench is then formed into the dielectric material layer and the silicon based substrate, and thereafter a dielectric material spacer is formed, in addition to the dielectric remaining on the field of the substrate, as well as along a sidewall of the 3D trench, and on a first portion of a sub-surface of the silicon based substrate that is present at a bottom of the 3D trench. A second portion of the sub-surface of the silicon based substrate that is present in the 3D trench remains physically exposed. Active energy storage device materials can then be formed laterally adjacent to the dielectric material spacer that is within the 3D trench and on the dielectric material layer.

A method of fabricating a porous wafer battery comprises the steps of providing a silicon wafer comprising a plurality of pores; applying a first metallization process; applying a passivation process; applying solder balls, aligning the silicon wafer with a substance, and applying a solder reflow process. A method using a porous wafer battery comprises the steps of connecting the porous wafer battery to a plurality of sensors, a plurality of switches, and a battery management system; monitoring temperature, resistance, or current; and electrically disconnecting a non-properly functioning pore.

A chip comprises a porous wafer battery and a device. The chip further comprises a wafer containing the device and at least a portion of the porous wafer battery. The wafer comprises a silicon substrate. The silicon substrate comprises a first region and a second region. The first region comprises a plurality of pores of the porous wafer battery. The second region 345 comprises a trench to accommodate a gate electrode of the device. A method of fabrication a chip comprising the steps of providing a substrate comprising a plurality of doped regions; patterning a mask on a front surface of the substrate; applying an etching process forming the plurality of pores in the first region of the substrate and the trench in the second region of the substrate; and then removing the mask.