A millimeter-wave active antenna unit and an interconnection structure between PCBs is provided. The interconnection structure between PCBs comprises a mainboard and an AIP antenna module. The mainboard is a first multilayer PCB on which a signal transmission line and a first pad electrically connected to the signal transmission line are provided. The AIP antenna module is a second multilayer PCB on which a second pad, an impedance matching transformation branch, an impedance line and a signal processing circuit are provided. The mainboard and the AIP antenna module are interconnected by directly welding multiple PCBs.

A system configured to increase a reliability of electrical connections in a device. The system including a lead configured to electrically connect a pad of at least one support structure to a pad of at least one electrical component. The lead includes an upper portion that includes a lower surface arranged on a lower surface thereof. The lower surface of the upper portion is arranged vertically above a first upper surface of a first pad connection portion; and the lower surface of the upper portion is arranged vertically above a second upper surface of the second pad connection portion. A process configured to increase a reliability of electrical connections in a device is also disclosed.

A microelectronics H-frame device comprising an RF crossover includes: a stack of two or more substrates, wherein a bottom surface of a top substrate comprises top substrate bottom metallization, and wherein a top surface of a bottom substrate comprises bottom substrate top metallization, wherein the top substrate bottom metallization and the bottom substrate top metallization form a ground plane that provides isolation to allow a first signal line to traverse one or more of the top substrate and the bottom substrate without being disturbed by a second signal line traversing one or more of the top substrate and the bottom substrate at a non-zero angle relative to the first signal line, at least one of the first signal line and the second signal line passing to a second level with the protection of the ground plane, thereby providing isolation from the other signal line.

A microelectronics H-frame device includes: a stack of two or more substrates wherein the substrate stack comprises a top substrate and a bottom substrate, wherein bonding of the top substrate to the bottom substrate creates a vertical electrical connection between the top substrate and the bottom substrate, wherein the top surface of the top substrate comprises top substrate top metallization, wherein the bottom surface of the bottom substrate comprises bottom substrate bottom metallization; mid-substrate metallization located between the top substrate and the bottom substrate; a micro-machined top cover bonded to a top side of the substrate stack; and a micro-machined bottom cover bonded to a bottom side of the substrate stack.

A component carrier includes a first stack having at least one first electrically insulating layer structure and at least one first electrically conductive layer structure, and a second stack with at least one second electrically insulating layer structure and at least one second electrically conductive layer structure. The first stack and the second stack are connected with each other so that a vertical two-dimensional electrically conductive connection is established. The first stack has a first cavity and the second stack has a second cavity, the first cavity and the second cavity being separated by at least one further electrically insulating layer structure. At least one of the first cavity and the second cavity is delimited by a wall being at least partially lined with an electrically conductive coating.

An antenna module includes a dielectric substrate, a plurality of antenna elements, and an RFIC having a plurality of power supply terminals configured to supply power to each of the plurality of antenna elements via a power supply line. The plurality of antenna elements include a first antenna element and a second antenna element disposed along a first direction connecting two points within a region, the first antenna element is located on the side of a center of the region relative to the second antenna element, and the number of antenna elements to which power is supplied by a power supply line for supplying power to the first antenna element is smaller than the number of antenna elements to which power is supplied by a power supply line for supplying power to the second antenna element.

A memory system includes a printed circuit board, at least one memory chip mounted on the printed circuit board, and a memory controller arranged on the printed circuit board and connected to 2.sup.N (where N is an integer of 2 or more) channels, the memory controller configured to perform a write operation and a read operation on the at least one memory chip. In the printed circuit board, a first subset of the channels corresponds to a first channel group configured in a point to point topology, and a remaining subset of the channels corresponds to a second channel group configured in a daisy chain topology.

A memory system includes a printed circuit board, at least one memory chip mounted on the printed circuit board, and a memory controller arranged on the printed circuit board and connected to 2.sup.N (where N is an integer of 2 or more) channels, the memory controller configured to perform a write operation and a read operation on the at least one memory chip. In the printed circuit board, a first subset of the channels corresponds to a first channel group configured in a point to point topology, and a remaining subset of the channels corresponds to a second channel group configured in a daisy chain topology.

A system configured to increase a reliability of electrical connections in a device. The system including a lead configured to electrically connect a pad of at least one support structure to a pad of at least one electrical component. The lead includes an upper portion that includes a lower surface arranged on a lower surface thereof. The lower surface of the upper portion is arranged vertically above a first upper surface of a first pad connection portion; and the lower surface of the upper portion is arranged vertically above a second upper surface of the second pad connection portion. A process configured to increase a reliability of electrical connections in a device is also disclosed.

A transmission line assembly is configured such that (i) a first target inner layer is one of second to (N−1)-th pattern layers selected therefrom, and (ii) a second target inner layer is another one of the second to (N−1)-th pattern layers selected therefrom; the second to (N−1)-th pattern layers except for the first and second target inner layers are referred to as inner layers. The transmission line assembly includes band-like first and second slits formed through the ground pattern of a corresponding one of the first and second target inner layers to expose a part of one of dielectric layers; the one of the dielectric layers is adjacent to the corresponding one of the first and second target inner layers. Each of the first and second slits has an edge facing the interlayer line, and the edge of each of the first and second slits is concavely curved toward the interlayer line.