Provided is a waveguide module for improving insertion loss and return loss. The waveguide module includes a metal jig including a waveguide through which a radio wave is transmitted and received formed therein, a chip disposed on the waveguide formed in the metal jig and including a plurality of circuits that is configured to transmit and receive radio waves inside the waveguide, and a circuit board configured to provide a bias used for an operation of the chip, wherein the metal jig includes a trench structure to dispose a radio wave absorber on a side surface of the chip in a direction crossing the waveguide.

According to one embodiment, a semiconductor device includes a first transistor and a second transistor. The first transistor includes a first end, a second end, and a first body. The second transistor includes a third end coupled to the second end, a fourth end, and a second body. The semiconductor device includes a first resistor coupled to the first end, a second resistor coupled between the first resistor and the second end, a third resistor coupled to the third end, a fourth resistor coupled between the third resistor and the fourth end, a first diode coupled between the first body and a node coupling the third resistor and the fourth resistor, and a second diode coupled between the second body and a node coupling the first resistor and the second resistor.

A dual-band filtering switch based on a single quad-mode dielectric resonator (DR) includes: a first printed circuit board (PCB) provided thereon with an input terminal; a second PCB provided thereon with an output terminal; a shielding shell arranged between the first and second PCBs and enclosing a shielding cavity together with the first and second PCBs; and a single quad-mode DR arranged in the shielding cavity. The first and second PCBs each include a feeding layer, a dielectric layer, and a ground layer that are stacked in sequence. The feeding layers of the first and second PCBs each include a microstrip line and a switching circuitry connected to the microstrip line, and the feeding layer is in contact with a surface of the DR to realize a switching function of the filtering switch. The proposed filtering switch feature low loss transmission and high selectivity with dual-band operation, miniaturization with the fewest resonators and friendly-integration, simultaneously.

A dual-band filtering switch based on a single quad-mode dielectric resonator (DR) includes: a first printed circuit board (PCB) provided thereon with an input terminal; a second PCB provided thereon with an output terminal; a shielding shell arranged between the first and second PCBs and enclosing a shielding cavity together with the first and second PCBs; and a single quad-mode DR arranged in the shielding cavity. The first and second PCBs each include a feeding layer, a dielectric layer, and a ground layer that are stacked in sequence. The feeding layers of the first and second PCBs each include a microstrip line and a switching circuitry connected to the microstrip line, and the feeding layer is in contact with a surface of the DR to realize a switching function of the filtering switch. The proposed filtering switch feature low loss transmission and high selectivity with dual-band operation, miniaturization with the fewest resonators and friendly-integration, simultaneously.

An integrated circuit (IC) includes a first switch, a second switch, and an amplifier electrically connected between the first switch and the second switch. An RF signal path passes through first switch, the amplifier, and the second switch in this order. The IC includes an input terminal and an output terminal that are to be connected to each other between the first switch and the amplifier or between the amplifier and the second switch outside of the IC with a component connected therebetween. In a top view of the IC, a first region of the first switch, a second region of the amplifier, and a third region of the second switch are disposed on a straight line such that a virtual straight line connects any point of the first region, any point of the second region, and any point of the second region in this order.

An integrated circuit (IC) includes a first switch, a second switch, and an amplifier electrically connected between the first switch and the second switch. An RF signal path passes through first switch, the amplifier, and the second switch in this order. The IC includes an input terminal and an output terminal that are to be connected to each other between the first switch and the amplifier or between the amplifier and the second switch outside of the IC with a component connected therebetween. In a top view of the IC, a first region of the first switch, a second region of the amplifier, and a third region of the second switch are disposed on a straight line such that a virtual straight line connects any point of the first region, any point of the second region, and any point of the second region in this order.

This application provides a semiconductor switch device, a manufacturing method thereof, and a solid-state phase shifter. The semiconductor switch device includes a first semiconductor layer, intrinsic layers, and second semiconductor layers that are stacked. There are at least two intrinsic layers. The second semiconductors are in a one-to-one correspondence with the intrinsic layers, and each second semiconductor layer is stacked on a side of a corresponding intrinsic layer away from the first semiconductor layer. The first semiconductor layer forms one PIN diode together with each first intrinsic layer and each second semiconductor layer. Any two adjacent PIN diodes are electrically isolated. Automatic parameter matching between the two PIN diodes is implemented by using a geometrically symmetric figure with centers of the two PIN diodes aligned, to improve linearity. In addition, the entire semiconductor switch device has a compact structure, to improve an integration degree and reduce costs.

A transmit/receive switching assembly includes a symmetrical PIN diode-based switch to selectively connect an antenna port to one of a transmit port and a receive port, transmit bias control circuitry that receives a first bias control signal, receive bias control circuitry that receives a second bias control signal, and shunt bias control circuitry coupled between the symmetrical PIN diode-based switch and a reference node. The first and second bias control signals are simultaneously and oppositely switchable between first and second voltage values and together configured to operate the switch between a transmit mode where RF signal flow is enabled from the transmit port to the antenna port and isolation is provided between the antenna port and the receive port, and a receive mode where RF signal flow is enabled from the antenna port to the receive port and isolation is provided between the antenna port and the transmit port.

A transmit/receive switching assembly includes a symmetrical PIN diode-based switch to selectively connect an antenna port to one of a transmit port and a receive port, transmit bias control circuitry that receives a first bias control signal, receive bias control circuitry that receives a second bias control signal, and shunt bias control circuitry coupled between the symmetrical PIN diode-based switch and a reference node. The first and second bias control signals are simultaneously and oppositely switchable between first and second voltage values and together configured to operate the switch between a transmit mode where RF signal flow is enabled from the transmit port to the antenna port and isolation is provided between the antenna port and the receive port, and a receive mode where RF signal flow is enabled from the antenna port to the receive port and isolation is provided between the antenna port and the transmit port.

The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed over the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.