H01S5/0042

SURFACE-EMITTING LASER MEASURING METHOD, MANUFACTURING METHOD, MEASURING APPARATUS, AND NON-TRANSITORY COMPUTER-READABLE MEDIUM
20220069548 · 2022-03-03 · ·

A surface-emitting laser measuring method includes the steps of causing at least one surface-emitting laser to emit light; and measuring a light intensity and a spectrum of the at least one surface-emitting laser by splitting the light emitted from the at least one surface-emitting laser in the step of causing the at least one surface-emitting laser to emit light and causing one split beam to be incident on a light-intensity measuring unit while causing another split beam to be incident on a spectrum measuring unit.

Emitter oxidation uniformity within a wafer

A wafer may comprise a substrate layer and a plurality of vertical cavity surface emitting lasers (VCSELs) formed on or within the substrate layer. A respective trench-to-trench distance associated with the plurality of VCSELs may vary across the wafer based on a predicted variation of an oxidation rate of an oxidation layer across the wafer.

VERTICAL-CAVITY SURFACE-EMITTING LASER FABRICATION ON LARGE WAFER
20210313770 · 2021-10-07 ·

Methods for fabricating vertical cavity surface emitting lasers (VCSELs) on a large wafer are provided. An un-patterned epi layer form is bonded onto a first reflector form. The first reflector form includes a first reflector layer and a wafer of a first substrate type. The un-patterned epi layer form includes a plurality of un-patterned layers on a wafer of a second substrate type. The first and second substrate types have different thermal expansion coefficients. A resulting bonded blank is substantially non-varying in a plane that is normal to an intended emission direction of the VCSEL. A first regrowth is performed to form first regrowth layers, some of which are patterned to form a tunnel junction pattern. A second regrowth is performed to form second regrowth layers. A second reflector form is bonded onto the second regrowth layers, wherein the second reflector form includes a second reflector layer.

TEMPERATURE CONTROL FOR BOTTOM-EMITTING WAFER-LEVEL VERTICAL CAVITY SURFACE EMITTING LASER TESTING
20210223310 · 2021-07-22 ·

A testing device may include a stage associated with holding an emitter wafer during testing of an emitter. The stage may be arranged such that light emitted by the emitter passes through the stage. The testing device may include a heat sink arranged such that the light emitted by the emitter during the testing is emitted in a direction away from the heat sink, and such that a first surface of the heat sink is near a surface of the emitter wafer during the testing but does not contact the surface of the emitter wafer. The testing device may include a probe card, associated with performing the testing of the emitter, that is arranged over a second surface of the heat sink such that, during the testing of the emitter, a probe of the probe card contacts a probe pad for the emitter through an opening in the heat sink.

Laser integration into a silicon photonics platform

The present disclosure provides for laser integration into photonic platforms in which a first wafer, including a first substrate and a first insulator that includes a first plurality of dies that each include a first set of optical waveguides, is bonded to a second wafer, including a second substrate and a second insulator that includes a second plurality of dies that each include a second set of optical waveguides. The bond between the two wafers defines a wafer bond interface joining the first insulator with the second insulator and vertically aligning the first plurality of dies with the second plurality of dies such that respective first sets of optical waveguides are optically coupled with respective second sets of optical waveguides.

Semiconductor laser wafer and semiconductor laser

A semiconductor laser wafer includes a substrate, a first semiconductor layer, an active layer, a second semiconductor layer, and a composition evaluation layer. The active layer is provided on the first semiconductor layer; multiple periods of pairs of a light-emitting multi-quantum well region and an injection multi-quantum well region are stacked in the active layer; the light-emitting multi-quantum well region is made of a first compound semiconductor and a second compound semiconductor. The second semiconductor layer is provided on the active layer. The composition evaluation layer is provided above the active layer and includes a first film and a second film; the first film is made of the first compound semiconductor and has a first thickness; and the second film is made of the second compound semiconductor and has a second thickness.

LIGHT SOURCE FOR INTEGRATED SILICON PHOTONICS
20210265805 · 2021-08-26 ·

A light source based on integrated silicon photonics includes a die of a silicon substrate having at least one chip site configured with a surface region, a trench region, and a first stopper region located separately between the surface region and the trench region. The trench region is configured to be a depth lower than the surface region. The light source includes a laser diode chip having a p-side facing the chip site and a n-side being distal to the chip site. The p-side includes a gain region bonded to the trench region, an electrode region bonded to the surface region, and an isolation region engaged with the stopper region to isolate the gain region from the electrode region. The light source also includes a conductor layer in the die configured to connect the gain region to an anode electrode and separately connect the electrode region to a cathode electrode.

Semiconductor layer structure with a thick buffer layer
11038320 · 2021-06-15 · ·

A semiconductor layer structure may include a substrate, a buffer layer formed on the substrate, and a set of epitaxial layers formed on the buffer layer. The buffer layer may have a thickness that is greater than 2 micrometers (μm). The set of epitaxial layers may include a quantum well layer. A quantum well intermixing region may be formed in association with the quantum well layer and a material diffused from a region of a surface of the semiconductor layer structure.

SURFACE-MOUNT COMPATIBLE VCSEL ARRAY
20210194217 · 2021-06-24 ·

A VCSEL/VECSEL array design is disclosed that results in arrays that can be directly soldered to a PCB using conventional surface-mount assembly and soldering techniques for mass production. The completed VCSEL array does not need a separate package and no precision sub-mount and flip-chip bonding processes are required. The design allows for on-wafer probing of the completed arrays prior to singulation of the die from the wafer. Embodiments relate to semiconductor devices, and more particularly to multibeam arrays of semiconductor lasers for high power and high frequency applications and methods of making and using the same.

Surface-mount laser apparatus and output optical power monitoring method

Embodiments of the present disclosure relate to a surface-mount laser apparatus. One example apparatus includes an on-chip laser, a passive waveguide, and a waveguide detector. The waveguide detector includes a first ridge waveguide. The on-chip laser includes a second ridge waveguide. The on-chip laser is coupled with the passive waveguide by the second ridge waveguide, and the waveguide detector is coupled with the passive waveguide by the first ridge waveguide.