Apparatuses and methods for passively monitoring the integrity of current sensing devices and associated circuitry in protective devices such as Ground Fault Circuit Interrupters and Arc Fault Circuit Interrupters are provided. A protection circuit interrupter employs a capacitively coupled noise signal obtained by an arrangement of one or both of the line side arms relative to a Rogowski coil. The noise signal is monitored while the line and load sides of a protective circuit interrupter are disconnected, and the connection of the line and load sides disabled if the noise signal fails to correlate sufficiently to a reference noise cycle. When the line and load sides are connected, the RMS value of the observed current signal is monitored such that the line and load sides are disconnected if the observed current signal fails to meet an RMS threshold. The observed current signal is otherwise compensated by subtracting the reference noise cycle prior to monitoring for the fault condition applicable to the protective device.

A monitor circuit that monitors power delivered by an electrical utility or other source to a consumer. The device may be located at or near an entry point, such as near an electrical meter. The device senses a material change in voltage, and terminates power to the consumer until normal voltage is restored. The device automatically resets when normal voltage is restored, without need for a service call.

A monitor circuit that monitors power delivered by an electrical utility or other source to a consumer. The device may be located at or near an entry point, such as near an electrical meter. The device senses a material change in voltage, and terminates power to the consumer until normal voltage is restored. The device automatically resets when normal voltage is restored, without need for a service call.

A method for locating and clearing phase faults in a micro-grid in off-mode. The method includes determining a surveillance area of a microgrid having at least two busbars to monitor; determining all source feeders and load feeders of the surveillance area; acquiring measurement data comprising current magnitude for all source feeders and load feeders; and monitoring the at least two busbars in the surveillance area for a voltage dip in one of phase-to-phase or phase-to-neutral voltages. The method further includes, on detecting a voltage dip on the monitored busbars, determining a defect phase having a minimum phase-to-neutral voltage; and performing current analysis for the defect phase.

A system and method for detecting arc faults includes receiving, by a controller module, a first sensed power characteristic from a first power characteristic sensor at an output of an upstream electrical component, receiving, by the controller module, a second sensed power characteristic from the second power characteristic sensor at an input of a downstream electrical component, the input and output connected by a conductor, determining, by the controller module, a difference between the first and second sensed power characteristics, and providing indication of an arc fault at the conductor.

A system and method for detecting arc faults includes receiving, by a controller module, a first sensed power characteristic from a first power characteristic sensor at an output of an upstream electrical component, receiving, by the controller module, a second sensed power characteristic from the second power characteristic sensor at an input of a downstream electrical component, the input and output connected by a conductor, determining, by the controller module, a difference between the first and second sensed power characteristics, and providing indication of an arc fault at the conductor.

Methods, apparatus, systems and articles of manufacture are disclosed for preventing undesired triggering of short circuit or over current protection. An example apparatus includes an output terminal; a voltage detection device coupled to a voltage detection input terminal and the output terminal and including a voltage detection output coupled to a logic gate first input terminal; a pulse extender coupled between a logic gate output and a selecting node; a multiplexer coupled to the selecting node and configured to be coupled to a first protection circuit, a second protection circuit, and a driver; and a switch coupled between an input terminal and the output terminal and including a switch gate terminal coupled to the driver.

Methods, apparatus, systems and articles of manufacture are disclosed for preventing undesired triggering of short circuit or over current protection. An example apparatus includes an output terminal; a voltage detection device coupled to a voltage detection input terminal and the output terminal and including a voltage detection output coupled to a logic gate first input terminal; a pulse extender coupled between a logic gate output and a selecting node; a multiplexer coupled to the selecting node and configured to be coupled to a first protection circuit, a second protection circuit, and a driver; and a switch coupled between an input terminal and the output terminal and including a switch gate terminal coupled to the driver.

An input power supply selection circuit includes a load, at least one input power supply to provide an operation power supply for the load, an input selection circuit to select the at least one input power supply as the operation power supply for the load, a sensing and control module to control the input selection circuit to switch the operation power supply for the load, and a load switch branch to control the load to be connected or disconnected. The sensing and control module controls the load switch branch to be connected or disconnected, and when the load switch branch is disconnected, the load and the at least one input power supply are not electrically coupled. Therefore, a contact protection design is simplified and a switching capacity requirement of the load switch branch is lowered.

An electronic circuit includes: a first series-connection of DC link capacitors (C.sub.A1, . . . , C.sub.Am) and a second series-connection of DC link capacitors (C.sub.B1, . . . , C.sub.Bn) connected in parallel between DC bus bars (DC+, DC), wherein the first series has a first node (A) between the DC link capacitors thereof and the second series has a second node (B) between the DC link capacitors thereof; and a short-circuit module (301; 401, 407) configured to receive a voltage difference (UM) between the first node and the second node and to cause the DC bus bars short circuited in response to the received voltage difference being greater than a predetermined threshold.