A control circuit includes a detection module configured to detect an operating condition of a semiconductor switching device; a determining module configured to determine a gate allowable voltage of the semiconductor switching device based on the operating condition; and an output module configured to output a control signal to a driving power supply circuit of the semiconductor switching device based on the gate allowable voltage, to control the driving power supply circuit to provide a gate on voltage that is not higher than the gate allowable voltage and that is positively correlated with the gate allowable voltage for the semiconductor switching device. When the operating condition of the semiconductor switching device becomes better, the gate allowable voltage of the semiconductor switching device is increased.

A power device may have at least two capacitors in series with each other and in parallel with a DC power source. The power device may have at least a first converter that has at least a controller configured to balance a voltage of the at least two capacitors. The power device may have at least a second converter connected to the at least two capacitors. The second converter may have at least three input conductors, each connected to a terminal of the at least two capacitors. The second converter may have at least two output conductors. The second converter may have at least a switching circuit between the at least three input conductors and at least two output conductors. The second converter may have at least a controller configured to operate the switching circuit. The second converter may passively preserve the voltage balance between the at least two capacitors.

A power supply system includes a plurality of power conversion devices connected in parallel with each other, a load state detector to detect an operating state of a load connected to the DC system, and a command generator to generate a distribution voltage command Vref Each of the power conversion devices includes a DC voltage controller to generate an output power command Pdc_ref based on a voltage of the DC system and the distribution voltage command Vref, and an AC/DC converter to convert AC power received from the main power source based on the output power command Pdc_ref and output the converted power to the DC system. The command generator generates the distribution voltage command Vref such that loss of the load connected to the DC system is reduced, based on a detection result of the load state detector.

Provided is a switching circuit including an input terminal, a switching terminal, a ground terminal, a bootstrap terminal, a high side transistor connected to the input terminal and the switching terminal, a low side transistor connected to the switching terminal and the ground terminal, a bootstrap capacitor connected to the switching terminal and the bootstrap terminal, a bootstrap switch including a PMOS transistor, and a driver circuit that turns on the bootstrap switch in a period in which the low side transistor is on and that turns off the bootstrap switch in a period in which the low side transistor is off, in which the driver circuit includes a level shifter and a buffer, and the level shifter includes an output line, a first resistance, a first transistor, a second resistance, a third resistance, a second transistor, a third transistor, a first capacitor, and a fourth transistor.

A control circuit for a plurality of metal-oxide semiconductor field-effect transistors (MOSFETs) in a bridge circuit for rectifying an alternating current (AC) input to generate a direct-current (DC) output includes first and second high side controls and first and second low side controls for providing gate voltage signals to respective MOSFETs in the bridge circuit. Dead time controls are provided for establishing dead time intervals between activation of complementary MOSFETs in the bridge circuit. The low side controls provide gate voltage signals having sloped edges and the dead time controls include Zener diodes having reverse bias thresholds for determining the duration of the dead time intervals.

A fully isolated drive circuit to be used for regulating an output voltage across a load. The isolated drive circuit may charge, discharge, or preserve the load charge using a controller that controls one or more switches. The controller may operate a switch according to an internal/external clock or an external control signal received by the controller. The isolated drive circuit may be an effective solution to simplify the drive design and decrease the amount of energy dissipated by the drive, especially when the load, associated with the drive, requires a high input voltage level.

The present disclosure concerns a device including a first switch, a diode, and a passive resistive element electrically in series between conduction and control terminals of the first switch, a terminal of the diode located on the side of the first switch being coupled to a node of application of a potential variable with respect to the potential of said conduction terminal.

A switching mode power supply with an adaptive setting of a threshold valley voltage. The switching mode power supply decreases a reference auxiliary current when a valley value of a primary switching voltage across a primary switch is smaller than a first threshold valley voltage. And in addition, the switching mode power supply can increase the reference auxiliary current when the valley value of the primary switching voltage is larger than a second threshold valley voltage.

Provided is a transistor drive circuit that drives a transistor to be driven and has a configuration including a controller that performs control to cause to temporally vary a circuit parameter contributing to a rise time or a fall time of the transistor to be driven.

This application relates to a charging protection circuit. The charging protection circuit implements overcurrent protection by using a four-terminal NMOS switching transistor. In the solution provided in this application, floating management is performed on a Sub port of the four-terminal NMOS switching transistor. Specifically, when the four-terminal NMOS switching transistor is turned on, potential of the Sub port is pulled up, to avoid an excessively large internal resistance of the four-terminal NMOS switching transistor caused by an excessively large voltage between the Sub port and a drain of the four-terminal NMOS switching transistor. In addition, this application further provides a charging circuit and an electronic device.