A power conversion system includes a power conversion apparatus and a programming support apparatus connected to the power conversion apparatus. The power conversion apparatus includes power conversion circuitry, program storage that stores a control program configured to control the power conversion circuitry, and a control unit that controls the power conversion circuitry according to a control program. The programming support apparatus includes a display data generation unit that generates display data of a block diagram illustrating a content of the control program using a plurality of functional blocks, and a link indicating input and output of information between the functional blocks based on the control program stored in the program storage.

A converter operable to convert an input voltage at an input node to an output voltage at an output node coupled to a load by switching on and off a transistor at a switching frequency, the converter comprising: an error amplifier circuit having a first input coupled to a reference voltage, a second input coupled to the output node through a resistive divider, a first output operable to output a control current and a second output operable to output a current equivalent to the control current; a peak current comparator circuit having a first input coupled to the second output of the error amplifier circuit, a second input and an output, the second input is coupled to the input node through an inductor; an off-time timer circuit having an input coupled to the first output of the error amplifier circuit and an output, the off-time timer circuit operable to set the switching frequency based on the control current; and a control circuit having a first input coupled to the output of the peak current comparator circuit, a second input coupled to the output of the off-time timer circuit and an output coupled to a control terminal of the transistor.

According to an aspect, a power supply system includes a plurality of power stages including a first power stage and a second power stage. The power supply system includes a voltage regulator connected to the first power stage and the second power stage. The voltage regulator is configured to detect an analog temperature signal from at least one of the first power stage and the second power stage via a communication line. The analog temperature signal is detected within a first voltage range. The voltage regulator is configured to transmit a digital bit stream to the first power stage and the second power stage via the communication line. The digital bit stream includes one or more programmable power stage parameters. The digital bit stream has digital levels within a second voltage range.

Provided is a control apparatus including a sensing unit configured to output a short circuit sensing signal in response to sensing, in a turn-on period of a main switching device by a switching device for on control, of short circuit of the main switching device, a protection operation control unit configured to output an instruction signal of a short circuit protection operation at delayed timing relative to the short circuit sensing signal, and a protection unit configured to turn off the switching device for on control in response to the instruction signal, in which the protection operation control unit outputs the instruction signal in response to continuation of the short circuit sensing signal beyond a first reference time period.

A load control device for controlling the power delivered from an AC power source to an electrical load includes a thyristor, a gate coupling circuit for conducting a gate current through a gate of the thyristor, and a control circuit for controlling the gate coupling circuit to conduct the gate current through a first current path to render the thyristor conductive at a firing time during a half cycle. The gate coupling circuit is able to conduct the gate current through the first current path again after the firing time, but the gate current is not able to be conducted through the gate from a transition time before the end of the half-cycle until approximately the end of the half-cycle. The load current is able to be conducted through a second current path to the electrical load after the transition time until approximately the end of the half-cycle.

A secondary-side-controller for a QR flyback converter and method for operating the same are provided. Generally, the secondary-side-controller includes a driver configured to control a power-switch (PS) on a primary side of converter to turn on the PS when a sinusoidal input voltage to the converter is at one of a plurality of valleys, an analog-to-digital-converter (ADC) to read the input voltage, output voltage, and load current, and generate digital signals based thereon. A valley-controller coupled to the driver, ADC, a look-up-table and a pulse width modulator (PWM) receives the signals from the ADC and using the look-up-table determines at which valley of the plurality of valleys to couple a PWM signal from the PWM to the driver. The valley-controller is operable for each switching cycle of the PS to increment, decrement or leave unchanged the valley at which the PWM signal is coupled from the PWM to the driver.

A ramp generator for a constant on-time DC-DC converter, wherein the ramp generator is configured to reduce DC offset and smooth transitions between conduction modes. The ramp voltage generator includes a common voltage generator suitable for generating a common voltage; a first ramp voltage generation block suitable for generating a first ramp voltage responsive to a first switching signal and a control signal, wherein the first switching signal resets one or more valley points of the first ramp voltage to one or more valley points of the common voltage; and a second ramp voltage generation block suitable for generating a second ramp voltage responsive to a second switching signal, the first ramp voltage, and the control signal.

In order to protect an inverter from prohibited switching states, a monitor including monitoring inputs and monitoring outputs is provided. The monitoring inputs are connected to the control outputs in order to receive the switching patterns, and the monitoring outputs are connected to the power switches. The monitor is designed to compare a transition from a first switching pattern to a second switching pattern with a number of prohibited transitions and/or with a number of permitted transitions and block the second switching pattern in the event of a match with one of the prohibited transitions and/or in the event of a deviation from the number of permitted transitions and to output the second switching pattern to the power switches via the monitoring outputs in the event of a deviation from the number of prohibited transitions and/or in the event of a match with one of the permitted transitions.

A method performed by a control system of a power electronics converter. A first part of a grid-side current controller runs a first feedback control algorithm having a first control cycle time and includes at least proportional control using a proportional gain. A third part of the controller runs a third feedback control algorithm having the first control cycle time and acting on an output from the first control algorithm after SOA limits have been applied and includes counteracting the proportional control of the first feedback control algorithm. A second part of the controller runs a second feedback control algorithm having a second control cycle time, less than the first control cycle time, and acting on an output from the third control algorithm with the same polarity as the first control algorithm and includes proportional control using the proportional gain.

A switched power circuit to control a common-mode signal. The switched power circuit includes a first switch and a second switch configured to generate switch mode voltage between a first node and a second node. The switched power circuit further includes a feedback circuit that is configured to detect common-mode voltage generated between the first node and the second node by a first signal generated by the first switch and a second signal generated by the second switch, and incrementally adjust a timing parameter of the first signal to adjust the common-mode signal.