An electronic circuit has an output node that outputs a DC signal indicating a temporal change rate of a voltage of a measurement target node, a first capacitor and a first resistor that are connected in series between the measurement target node and a first reference voltage node, a second capacitor that is connected between the output node and a second reference voltage node, a first switch that switches whether or not to short-circuit the first reference voltage node and the output node, and a rectifier circuit that flows a current to a connection node between the first capacitor and the first resistor from the output node, and cuts off a current to the output node from the connection node.

A totem-pole PFC circuit is provided. The totem-pole PFC circuit includes an inductor, a first bridge arm and a second bridge arm. The first bridge arm includes a first switch and a second switch connected in series. A first middle node connected between the first and second switches is coupled to a first terminal of an AC power source through the inductor. The second bridge arm connected to the first bridge arm in parallel includes a third switch and a fourth switch connected in series. A second middle node connected between the third and fourth switches is coupled to a second terminal of the AC power source. When a polarity of the AC power source is changed, a change time of a voltage on the second middle node is longer than a preset time not less than 20 μs.

Provided is a driving apparatus that drives a switching device, the driving apparatus including a reference potential line, a first switching control unit configured to switch whether to connect a control terminal of the switching device to the reference potential line, a first resistor element arranged in series to the first switching control unit in a path from the control terminal of the switching device to the reference potential line, a first capacitor provided in parallel with the first resistor element in the path from the control terminal of the switching device to the reference potential line, and a discharge control unit configured to control whether to discharge the first capacitor.

The present invention provides a capacitor having a first structure made of a metal layer and a second structure made of the same metal layer and a dielectric layer between the first and the second metal structure, wherein the dielectric layer has a relative permittivity greater than 4, in particular greater than 6. It also provides a monolithically integrated circuit including such a capacitor and optionally other components. A method of manufacturing such a capacitor is also provided.

A differential-slope-limiting-switch and method are provided. Generally, the switch includes a first transistor having a first source-drain (SD) and well coupled to a first port of the switch, a gate, and a second SD, and a second transistor having a first SD and well coupled to a second port, a gate, and a second SD coupled to the second SD of the first transistor. A selector-circuit couples the gate of the first transistor to a first current-source when a signal to close the switch is received, and to the first port when it is not received. A second selector-circuit couples the gate of the second transistor to a second current-source when the signal is received, or to the second port. First and second feedback-capacitors couple each gate to the port on opposite sides of the switch and with the current-sources limit a slope of voltage transitions across the closed switch.

A modulation technique is described in which a controller modulates the output AC voltages to introduce an offset to the phase that is most positive or most negative such that the phase is clamped to the +dc supply when the respective phase is most positive and to the −dc supply rail when most negative. The offset is provided by introducing a common mode component voltage to all of the phases over a plurality of output angle segments. In order to reduce the Noise Vibration and Harshness (NVH) and EMI, the common mode component voltage amplitude is varied over the output angles within the respective segment between a minimum and a maximum in order to control a slew rate of the rising or falling edges of the three phase AC output voltages.

A controller for a power converter comprising a drive signal generator and drive strength control and a variable strength multi-stage gate driver. The drive signal generator and drive strength control outputs a drive signal to control switching of a power switch and a strength signal to control drive strength of the power switch. The variable strength multi-stage gate driver is configured to turn ON the power switch in response to the drive signal with a first drive strength then a second drive strength when the strength signal is not asserted. The variable strength multi-stage gate driver is configured to turn ON the power switch in response to the drive signal with a third drive strength then the second drive strength when the strength signal is asserted. The second drive strength is stronger than the first drive strength and the first drive strength is stronger than the third drive strength.

A method for operating a gate driver system includes measuring a first parameter according to a first priority schedule synchronously to a first edge of a switching signal generated by a gate driver integrated circuit and having a variable duty cycle. The method includes after measuring the first parameter of the gate driver system and prior to a second edge of the switching signal, measuring at least a second parameter of the gate driver system according to a first round-robin schedule synchronously to the first edge of the switching signal.

A method for validating operation of a driver integrated circuit includes providing a signal using an output node. The signal is provided using multiple set points in response to a change in state of an input signal. Each set point corresponds to a different phase of a multi-phase transition of the signal. The method includes providing a timer value at an end of a phase of the multi-phase transition and determining whether the signal is in a target signal range of the phase based on the timer value at the end of the phase, a predetermined value defining the target signal range of the phase, and a predetermined time limit for the phase. A current through the output node may be provided using the multiple set points, and a voltage on the output node may have the multi-phase transition.

A gate driver includes a variable strength driver circuit that provides an output signal to drive a high power device. The gate driver receives an update request from a host controller during an operating mode in which switching operations occur and updates one or more operating parameters associated with driving the high power device. The operating parameters including turn-on parameters, turn-off parameters, and soft shutdown parameters. The variable strength driver circuit uses the turn-on parameters for turn-on phases for the output signal, uses the turn-off parameters for turn-off phases for the output signal, and uses the soft shutdown parameters for soft shutdown phases for the output signal. The update request adjusts current, voltage, and/or time for one or more phases of the turn-on, turn-off and/or soft shutdown parameters.