A gate driver circuit includes at least one driver configured to generate a first gate control signal for a first power disconnect switch and a second gate control signal for a second power disconnect switch in parallel with the first power disconnect switch, and logic configured to implement a delayed turn on time for the second gate control signal compared to the first gate control signal such that the first power disconnect switch turns on before the second power disconnect switch when powering up a load coupled to the first and the second power disconnect switches. The gate driver circuit logic may also be configured to implement a delayed turn off time such that the first power disconnect switch turns off before the second power disconnect switch when powering down the load. Corresponding power conversion circuits, electronic systems, and methods of power disconnect switch control are also described.

A driving circuit for a semiconductor circuit which includes a pair of main terminals through which a main current is conducted and a control terminal to which a control voltage is applied to control a circulation state of the main current, includes: driving voltage switching circuitry that receives a control signal, instructs switching between driving voltages based on a change in the control signal, and outputs a driving voltage, among the driving voltages, that has been selected in the switching; low-speed control circuitry that instructs an increase-decrease change in the control voltage at a low speed; speed-increase control circuitry that executes a speed-increase control of increasing a speed of the increase-decrease change made by the low-speed control circuitry; and speed-increase switching circuitry that instructs switching between an execution and a non-execution of the speed-increase control, and instructs switching between levels of a speed-increase change caused by the speed-increase control.

In a switching converter, a controller has a controller input and a controller output. The controller is configured to provide: a first mode signal at the controller output responsive to a first temperature signal at the controller input; and a second mode signal at the controller output responsive to a second temperature signal at the controller input. Drive circuitry has a drive input and a drive output. The drive input is coupled to the controller output. The drive circuitry is configured to provide: a first drive signal at the drive output responsive to the first mode signal; and a second drive signal at the drive output responsive to the second mode signal. A switch has a control terminal coupled to the drive output.

A gate of the first p-type MOS transistor and the first and second control circuits are electrically coupled to a first node. The first control circuit lowers a voltage or the first node between a first time and a second time at which the first p-type MOS transistor is off. The second control circuit lowers the voltage of the first node between a third time and a fourth time at which the first p-type MOS transistor is on. The second time is later than the first time. The fourth time is later than the second and third times. The first p-type MOS transistor is turned on during a first period. A voltage decrease amount of the first node per unit time in the first control circuit is greater than that in the second control circuit.

A gate drive apparatus is provided. The gate drive apparatus includes a gate drive unit configured to drive a gate of a switching device; a parameter measuring unit configured to measure a parameter corresponding to current flowing through the switching device; a discrepancy detection unit configured to detect discrepancy between current flowing through the switching device during an on-state of the switching device and a reference value, based on the parameter; and a control unit that, if the discrepancy is not detected, switches a change speed of a gate voltage of the switching device at a timing when a reference time has elapsed since a turn-off start of the switching device during a next turn-off time period of the switching device, and if the discrepancy is detected, keeps the change speed of the gate voltage during the next turn-off time period of the switching device.

An electronic circuit has an output node that outputs a DC signal indicating a temporal change rate of a voltage of a measurement target node, a first capacitor and a first resistor that are connected in series between the measurement target node and a first reference voltage node, a second capacitor that is connected between the output node and a second reference voltage node, a first switch that switches whether or not to short-circuit the first reference voltage node and the output node, and a rectifier circuit that flows a current to a connection node between the first capacitor and the first resistor from the output node, and cuts off a current to the output node from the connection node.

An inverter device includes first and second input terminals, a series circuit having a plurality of switch elements coupled between the first and second input terminals. Each of the switch elements is coupled in parallel with a series circuit having a diode and an inductor.

An improved gate driver using a microcontroller (uC), a voltage selector (VS), an adjustable voltage regulator (AVR), and an auxiliary current sinking circuit (ACSC) to actively provide selectable drive signals either higher, lower or equal to the basic on voltage and off voltage drive signals for a selected semiconductor device thereby providing an active voltage-mode gate driver for actively speeding up or slowing both the on time and off time transitions of a semiconductor.

First and second FETs of a half-bridge are series connected between first and second terminals and are gate driven, respectively, by first and second drivers. An inductance is connected to the intermediate node of the half-bridge. Power supply for the second driver circuit is a supply voltage generated by a voltage regulator as a function of the voltage between the first and the second terminal. Power supply for the first driver circuit is a supply voltage generated by a bootstrap capacitor having a first terminal connected via a first switch to receive the supply voltage output from the voltage regulator and a second terminal connected to the intermediate node. The first terminal of the bootstrap capacitor is further connected by a second switch to receive a second supply voltage. A control circuit generates control signals for the first and second driver circuits and the first and second switches.

A drive device includes a driver configured to drive a high-side transistor and a low-side transistor; a first current detecting part for detecting one of an upper-side current that flows to the high-side transistor and a lower-side current that flows to the low-side transistor; a first current determining part that detects a sign of switching of a forward direction/reverse direction of the upper-side current or the lower-side current detected by the first current detecting part or the switching per se; and a slew rate adjusting part configured to control the driver such that a slew rate of the high-side transistor or the low-side transistor is adjusted according to a determination result of the first current determining part.