A control circuit for controlling a switching converter having a low quiescent current. The control circuit has an error amplifying circuit, an on time generator, a first comparing circuit and a second comparing circuit. When the switching converter operates in a light load operation mode, the error amplifying circuit and the on time generator are deactivated. Meanwhile, the first comparing circuit compares a current sensing signal indicative of inductor current with a current reference signal to provide an off time control signal during an on state of a low side switch to determine an on moment of a high side switch. The second comparing circuit compares the voltage feedback signal with a voltage reference signal to provide an on time control signal to determine an off moment of the high side switch.

A method, which is applied in a driving circuit including an analog-to-digital convertor (ADC) and a switching circuit including an inductor and coupled to a load, includes steps of: performing an analog-to-digital conversion on a load voltage of the load at a first rate; and producing at least a current pulse flowing through the inductor at a second rate. Wherein, each current pulse among the at least a current pulse is accomplished within a second cycle corresponding to the second rate, all of the at least a current pulse are accomplished within a first cycle corresponding to the first rate, and a first length of the first cycle is longer than twice of a second length of the second cycle.

A semiconductor device includes a layer structure including a first gate electrode and a second gate electrode, and a first main electrode and a second main electrode that can be electrically connected through the layer structure. The threshold voltage of the second gate electrode is higher than the threshold voltage of the first gate electrode. In the α state and the β condition, the switching operation is performed using the first gate electrode, and in the γ state or the δ condition, the switching operation is performed using the second gate electrode.

A switched capacitor voltage converter includes an inductive branch and two branches, by controlling a turning on and off of switch transistors, charges on a parasitic capacitor of one branch are completely transferred to another branch of the two branches via the inductive branch within a period of time after primary switch transistors are turned off, and voltage difference between both terminals of each of the primary switch transistors become zero, and then the primary switch transistors are started to be turned on, the respective voltage differences of the primary switch transistors are zero at a moment when the primary switch transistors are turned on.

A power module includes: a GaN transistor, an NMOS transistor, a first capacitor, a first diode and a second diode. The NMOS transistor is electrically connected to the GaN transistor. A negative electrode of the first capacitor is electrically connected to an anode of the first diode and a gate of the GaN transistor. A cathode of the second diode is electrically connected to a gate of the NMOS transistor. The power module further includes a power module control terminal electrically connected to an anode of the first capacitor and an anode of the second diode.

Controlling a charging current while transferring energy from a source battery to a target battery in an electric vehicle (EV) includes operating, by control circuitry, a buck converter at a fixed switching frequency to transfer power from the source battery to the target battery, in a first operational mode; in response to detecting a first trigger event, transitioning from the first operational mode to a second operational mode to operate the buck converter at a variable switching frequency; and in response to detecting a second trigger event, transitioning to a third operational mode to activate a boost converter coupled to the source battery and the target battery.

Techniques for a sinking and sourcing power stage are provided. In an example, a power stage circuit can include a first power transistor configured to couple to a first input power rail, a second power transistor configured to couple to a second input power rail, an output node configured to couple to a load and to couple the first power transistor in series with the second power transistor between the first and second input power rails, and a controller configured to operate the first and second power transistors in a first mode to source current to the load and to operate the first and second power transistors in a second mode to sink current from the load.

The present application discloses a power component of a three-level converter, a three-level converter and a wind turbine. The power component of the three-level converter includes: a first NPC bridge arm unit including a plurality of first NPC bridge arms connected in parallel; a second NPC bridge arm unit including a plurality of second NPC bridge arms connected in parallel; and a third NPC bridge arm unit including a plurality of third NPC bridge arms connected in parallel. The number of the second NPC bridge arms is the same as the number of the first NPC bridge arms, and the number of the third NPC bridge arms is determined based on the ratio of the loss of the first NPC bridge arm to the loss of the third NPC bridge arm.

A loss optimization control method for modular multilevel converters (MMCs) under fault-tolerant control is disclosed. The method includes the following steps: when a fault of a SM in a MMC occurs, bypassing the faulty SM to achieve fault-tolerant control; suppressing the fundamental circulating current using a fundamental circulating current controller; respectively calculating the loss of each SM in faulty arms and healthy arms by using loss expressions of different switching tubes in SMs of the MMC; aiming at the loss imbalance between the arms of the MMC, taking the loss of a healthy SM as the reference, adjusting the period of capacitor voltage sorting control in the faulty SMs, achieving the loss control over the working SMs in the faulty SMs, and finally achieving the loss balance of each SM in the faulty arms and the healthy arms. Compared with the conventional methods, the proposed method is easier to implement and does not increase the construction cost of MMCs.

A regenerative gate charging circuit includes an inductor coupled to a gate of a FET. An output control circuit is coupled to a timing control circuit and a bridged inductor driver, which is coupled to the inductor. A sense circuit is coupled to the gate and to the timing control circuit, which receives a control signal, generates output control signals in accordance with a first timing profile, and transmits the output control signals to the output control circuit. In accordance with the first timing profile, the output control circuit holds switches or controllable current sources of the bridged inductor driver in an ON state for a first period and holds the switches or controllable current sources in an OFF state for a second period. Gate voltages are sampled during the second period and after the first period. The timing control circuit generates a second timing profile using the sampled voltages.