SEMICONDUCTOR DEVICE, POWER CONVERSION APPARATUS, AND METHOD FOR DRIVING SEMICONDUCTOR DEVICE

Abstract

A semiconductor device includes a layer structure including a first gate electrode and a second gate electrode, and a first main electrode and a second main electrode that can be electrically connected through the layer structure. The threshold voltage of the second gate electrode is higher than the threshold voltage of the first gate electrode. In the α state and the β condition, the switching operation is performed using the first gate electrode, and in the γ state or the δ condition, the switching operation is performed using the second gate electrode.

Claims

1. A semiconductor device comprising: a layer structure; and a first main electrode and a second main electrode configured to be conducting through the layer structure, wherein the layer structure includes: a first semiconductor layer of a first conductivity type having a first surface and a second surface opposite the first surface; a first semiconductor region of a second conductivity type partially provided in a surface layer on the first surface; a second semiconductor region of a second conductivity type partially provided in a surface layer on the first surface; a second semiconductor layer of a first conductivity type partially provided in a surface layer in the first semiconductor region and a surface layer in the second semiconductor region; a first gate insulating film provided in contact with the first semiconductor region sandwiched between the first semiconductor layer and the second semiconductor layer; a second gate insulating film provided in contact with the second semiconductor region sandwiched between the first semiconductor layer and the second semiconductor layer; a first gate electrode being a gate electrode provided in contact with the first gate insulating film; and a second gate electrode being the gate electrode provided in contact with the second gate insulating film, applying a voltage to the first gate electrode or the second gate electrode makes it possible to switch between an ON state in which the first main electrode and the second main electrode are conducting through the layer structure and an OFF state in which the first main electrode and the second main electrode are not conducting through the layer structure, a threshold voltage of the second gate electrode is higher than a threshold voltage of the first gate electrode, α state in which a temperature of the layer structure is lower than a threshold temperature is defined as an α state, α state in which a temperature of the layer structure is equal to or higher than a threshold temperature is defined as a γ state, in the α state, a switching operation of switching to the ON state or the OFF state is performed using the first gate electrode, and in the γ state, the switching operation is performed using the second gate electrode.

2. The semiconductor device according to claim 1, wherein a condition that a switching current is less than a threshold current is defined as a β condition, the switching current being a current value during the switching operation, a condition that the switching current is equal to or larger than a threshold current is defined as a β condition, the switching operation is performed using the first gate electrode, in the α state and the β condition, and the switching operation is performed using the second gate electrode, in the γ state or the δ condition.

3. The semiconductor device according to claim 2, wherein the threshold current is ½ of a rated current.

4. The semiconductor device according to claim 1, wherein the threshold temperature is 75° C.

5. The semiconductor device according to claim 1, further comprising: a third semiconductor region of a second conductivity type partially provided in a surface layer on the second surface; a third semiconductor layer of a first conductivity type partially provided in a surface layer in the third semiconductor region; a third gate insulating film provided in contact with the third semiconductor region sandwiched between the first semiconductor layer and the third semiconductor layer; and a third gate electrode being the gate electrode formed in contact with the third gate insulating film.

6. The semiconductor device according to claim 1, wherein an impurity concentration in the second semiconductor region is higher than an impurity concentration in the first semiconductor region.

7. The semiconductor device according to claim 1, wherein a thickness of the second gate insulating film is larger than a thickness of the first gate insulating film.

8. The semiconductor device according to claim 1, wherein a dielectric constant of the second gate insulating film serving as a channel is lower than a dielectric constant of the first gate insulating film serving as a channel.

9. The semiconductor device according to claim 1, wherein a gate length of the second gate electrode is larger than a gate length of the first gate electrode.

10. The semiconductor device according to claim 1, wherein a threshold voltage of the second gate electrode is higher, by 10% or more, than a threshold voltage of the first gate electrode.

11. The semiconductor device according to claim 1, further comprising a fourth semiconductor region of a second conductivity type partially provided in a surface layer on the first surface, wherein the second semiconductor layer is also partially provided in a surface layer in the fourth semiconductor region, the semiconductor device further comprising: a fourth gate insulating film provided in contact with the fourth semiconductor region sandwiched between the first semiconductor layer and the second semiconductor layer; and a fourth gate electrode being the gate electrode provided in contact with the fourth gate insulating film, wherein a threshold voltage of the fourth gate electrode is equal to or higher than a threshold voltage of the first gate electrode.

12. The semiconductor device according to claim 11, wherein a threshold voltage of the fourth gate electrode is equal to or less than a threshold voltage of the second gate electrode.

13. The semiconductor device according to claim 1, wherein after the switching operation for switching to the ON-state is performed, a voltage applied to the gate electrode not used for the switching operation is switched.

14. A power conversion apparatus comprising: a conversion circuit including the semiconductor device according to claim 1, the conversion circuit configured to convert and output input power; a drive circuit configured to output a drive signal for driving the semiconductor device to the semiconductor device; and a control circuit configured to output a control signal for controlling the drive circuit to the drive circuit.

15. A method for driving a semiconductor device, wherein the semiconductor device includes: a layer structure; and a first main electrode and a second main electrode configured to be conducting through the layer structure, the layer structure includes: a first semiconductor layer of a first conductivity type having a first surface and a second surface opposite the first surface; a first semiconductor region of a second conductivity type partially provided in a surface layer on the first surface; a second semiconductor region of a second conductivity type partially provided in a surface layer on the first surface; a second semiconductor layer of a first conductivity type partially provided in a surface layer in the first semiconductor region and a surface layer in the second semiconductor region; a first gate insulating film provided in contact with the first semiconductor region sandwiched between the first semiconductor layer and the second semiconductor layer; a second gate insulating film provided in contact with the second semiconductor region sandwiched between the first semiconductor layer and the second semiconductor layer; a first gate electrode being a gate electrode provided in contact with the first gate insulating film; and a second gate electrode being the gate electrode provided in contact with the second gate insulating film, applying a voltage to the first gate electrode or the second gate electrode makes it possible to switch between an ON state in which the first main electrode and the second main electrode are conducting through the layer structure and an OFF state in which the first main electrode and the second main electrode are not conducting through the layer structure, a threshold voltage of the second gate electrode is higher than a threshold voltage of the first gate electrode, α state in which a temperature of the layer structure is lower than a threshold temperature is defined as an α state, α state in which a temperature of the layer structure is equal to or higher than the threshold temperature is defined as a γ state, in the α state, a switching operation of switching to the ON state or the OFF state is performed using the first gate electrode, and in the γ state, the switching operation is performed using the second gate electrode, the method comprising switching a voltage applied to the gate electrode not used for the switching operation, before performing the switching operation for switching to the OFF state.

16. The method for driving a semiconductor device according to claim 15, wherein a condition that a switching current is less than a threshold current is defined as a β condition, the switching current being a current value during the switching operation, a condition that the switching current is equal to or larger than a threshold current is defined as a δ condition, the switching operation is performed using the first gate electrode, in the α state and the β condition, and the switching operation is performed using the second gate electrode, in the γ state or the δ condition.

17. The method for driving a semiconductor device according to claim 15, wherein the semiconductor device further includes: a third semiconductor region of a second conductivity type partially provided in a surface layer on the second surface; a third semiconductor layer of a first conductivity type partially provided in a surface layer in the third semiconductor region; a third gate insulating film provided in contact with the third semiconductor region sandwiched between the first semiconductor layer and the third semiconductor layer; and a third gate electrode being the gate electrode formed in contact with the third gate insulating film.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] FIG. 1 is a plan view schematically showing an example of a configuration of an emitter electrode surface of a multi-gate IGBT being an example of a multi-gate semiconductor device including a plurality of gates;

[0023] FIG. 2 is a cross-sectional view schematically showing an example of a configuration taken along line I-I′ in FIG. 1;

[0024] FIG. 3 is a diagram for illustrating a method for driving the multi-gate semiconductor device according to the preferred embodiment;

[0025] FIG. 4 is a cross-sectional view schematically showing another configuration example of the multi-gate semiconductor device according to the preferred embodiment;

[0026] FIG. 5 is a cross-sectional view schematically showing a configuration example of the multi-gate semiconductor device according to the preferred embodiment;

[0027] FIG. 6 is a cross-sectional view schematically showing a configuration example of the multi-gate semiconductor device according to the preferred embodiment; and

[0028] FIG. 7 is a diagram conceptually showing an example of the configuration of a power conversion system including a power conversion apparatus according to the present preferred embodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] Hereinafter, preferred embodiments will be described with reference to the accompanying drawings. In the following preferred embodiments, detailed features and the like are also shown for the description of the technique, but they are merely examples, and not all of them are necessarily essential features for enabling the preferred embodiments to be carried out.

[0030] It should be noted that the drawings are schematically shown, and for convenience of description, omission of the configuration, simplification of the configuration, or the like may be made in the drawings as appropriate. In addition, the mutual relationship between the sizes and positions of the respective configurations shown in the different drawings is not necessarily described accurately and can be appropriately changed. In addition, in drawings such as plan views other than cross-sectional views, hatching may be added in order to facilitate understanding of the contents of the preferred embodiments.

[0031] In addition, in the following description, the same components are denoted by the same reference numerals to be illustrated, and their names and functions are also the same. Therefore, detailed descriptions thereof may be omitted to avoid redundancy.

[0032] In addition, in the description given in the present specification, when description such as “comprising”, “including”, or “having” a certain component is made, it is not an exclusive expression excluding the presence of other components unless otherwise noted.

[0033] In addition, in the description given in the present specification, ordinal numbers such as “first” or “second” may be used, but these terms are used to facilitate understanding of the contents of the preferred embodiments for convenience, and the contents of the preferred embodiments are not limited to the order or the like that can be generated by these ordinal numbers.

[0034] In addition, in the description given in the present specification, in the expression such as “ . . . axis positive direction” or “ . . . axis negative direction”, a direction along the arrow of the . . . axis shown is a positive direction, and a direction opposite to the arrow of the . . . axis shown is a negative direction.

[0035] In addition, in the description given in the present specification, terms that mean a specific position or direction such as “upper”, “lower”, “left”, “right”, “side”, “bottom”, “front”, or “back” may be used, but these terms are used to facilitate understanding of the contents of the preferred embodiments for convenience and the preferred embodiments are not related to the position or direction at the time of actual implementation.

[0036] In addition, in the description given in the present specification, when it is described as “the upper surface of . . . ”, “the lower surface of . . . ”, or the like, it is assumed to include a state in which another component is formed on the upper surface or the lower surface of the target component in addition to the upper surface itself or the lower surface itself of the target component. That is, for example, the description “B provided on the upper surface of A” does not preclude the interposition of another component “C” between A and B.

First Preferred Embodiment

[0037] Hereinafter, a semiconductor device and a method for driving the semiconductor device according to the present preferred embodiment will be described.

[0038] It should be noted that in the description hereinafter, regarding a conductivity type of an impurity, it is assumed that a first conductivity type is n-type and a second conductivity type is p-type.

[0039] In addition, in the following description, the expression “A and B are electrically connected” means that a current can flow bidirectionally between the configuration A and the configuration B.

[0040] <Configuration of Semiconductor Device>

[0041] In the following preferred embodiments, an insulated gate (gate control) semiconductor device will be described.

[0042] FIG. 1 is a plan view schematically showing an example of a configuration of an emitter electrode surface of a multi-gate (that is, MG)-IGBT being an example of a multi-gate semiconductor device including a plurality of gates. In addition, FIG. 2 is a cross-sectional view schematically showing an example of a configuration taken along line I-I′ in FIG. 1.

[0043] In the present preferred embodiment, two gates are provided on a first main surface (emitter surface) of an n-type semiconductor substrate 30 having two main surfaces, and the two gates have an enhancement n-channel metal-oxide-semiconductor field-effect transistor (that is, MOSFET) structure.

[0044] An MG-IGBT element 31 is provided on the n-type semiconductor substrate 30, and a termination structure 32 for suppressing electric field concentration is provided around the MG-IGBT element 31.

[0045] In the present preferred embodiment, as the semiconductor substrate 30, for example, an n-type (n.sup.−) single crystal bulk silicon substrate (FZ wafer) having an impurity concentration of about 1×10.sup.14 cm.sup.−3 is adopted. The semiconductor substrate 30 functions as an n-type base layer 1 of the MG-IGBT element 31.

[0046] The surface layer on the first main surface (emitter surface) of the semiconductor substrate 30 of the MG-IGBT element 31 is formed with a p-type base region 3. The p-type base region 3 includes a p-type base region 3a and a p-type base region 3b having an impurity concentration higher than the impurity concentration of the p-type base region 3a. The p-type base region 3a and the p-type base region 3b, provided on the emitter surface and formed in the surface layer of the n-type base layer 1, are arranged alternately with each other as shown with an example in FIG. 2.

[0047] The p-type base region 3a is formed with a trench 4a that penetrates the p-type base region 3a and further reaches the inside of the n-type base layer 1. Similarly, the p-type base region 3b is formed with a trench 4b that penetrates the p-type base region 3b and further reaches the inside of the n-type base layer 1.

[0048] The bottom surface and the side surface in the trench 4a are formed with a gate insulating film 6a. In addition, an inner region surrounded by the gate insulating film 6a in the trench 4a is filled with, for example, polysilicon having an impurity concentration of about 1×10.sup.20 cm.sup.−3, and a gate electrode 7a is formed.

[0049] Similarly, the bottom surface and the side surface in the trench 4b are formed with a gate insulating film 6b. In addition, an inner region surrounded by the gate insulating film 6b in the trench 4b is filled with, for example, polysilicon having an impurity concentration of about 1×10.sup.20 cm.sup.−3, and a gate electrode 7b is formed.

[0050] In addition, the mesa shape 13 (that is, the p-type base region sandwiched between the adjacent trenches) partitioned by the trench 4a and the trench 4b is arranged with a p-type base region 3a and a p-type base region 3b. These structures are repeatedly arranged with the p-type base region 3a, the trench 4a, the p-type base region 3a, the p-type base region 3b, the trench 4b, and the p-type base region 3b in this order along the X-axis positive direction in FIG. 2.

[0051] In addition, the surface layer in the p-type base region 3a is selectively formed with an n-type (n.sup.+) emitter layer 5a adjacent to a part of the side surface portion of the gate electrode 7a. In addition, the surface layer in the p-type base region 3b is selectively formed with an n-type (n.sup.+) emitter layer 5b adjacent to a part of the side surface portion of the gate electrode 7b.

[0052] Here, the mesa shape 13 in which the n.sup.+-type emitter layer 5a and the n.sup.+-type emitter layer Sb are formed is also referred to as a mesa 13a. In addition, the mesa shape 13 in which the n.sup.+-type emitter layer 5a and the n.sup.+-type emitter layer Sb are not formed is also referred to as a mesa 13h. The mesa 13a and the mesa 13b are alternately arranged in the X-axis positive direction in FIG. 2.

[0053] In the present preferred embodiment, the n.sup.+-type emitter layer 5a and the n.sup.+-type emitter layer 5b have a thickness of about 0.5 μm and an impurity concentration of about 3×10.sup.19 cm.sup.−3.

[0054] The p-type base region 3a facing the gate electrode 7a in the mesa 13a functions as a first channel formation region. In addition, the p-type base region 3b facing the gate electrode 7b in the mesa 13a functions as a second channel formation region.

[0055] The upper surface of the n-type base layer 1 is partially formed with an insulating film 8. In addition, an emitter electrode 9 is formed to cover the insulating film 8 and the upper surface (that is, a part of the upper surface of the mesa 13a) of the n-type base layer 1 exposed without being covered with the insulating film 8. The emitter electrode 9 is further connected to the emitter terminal 90.

[0056] On the upper surface of the mesa 13a, the p-type base region 3a, the p-type base region 3b, the n.sup.+-type emitter layer 5a, and the n.sup.+-type emitter layer 5b are electrically connected to the emitter electrode 9.

[0057] On the other hand, since covered with the insulating film 8, the upper surfaces of the trench 4a, the trench 4b, and the mesa 13b are insulated and separated from the emitter electrode 9. However, a small area of the upper surface of the mesa 13b is connected to the emitter electrode 9 and has contact resistance (not shown here).

[0058] As shown with an example in FIG. 1, a gate pad 11 and a gate pad 12 insulated and separated from the emitter electrode 9 are disposed on a first main surface (emitter surface) of the n-type semiconductor substrate 30.

[0059] The gate pad 11 is made of an aluminum-based material. The gate pad 11 is electrically connected to the gate electrode 7a through the trench routing wiring line 4c.

[0060] The gate pad 12 is made of an aluminum-based material. The gate pad 12 is electrically connected to the gate electrode 7b through the trench routing wiring line 4d. The trench routing wiring line 4c has a trench structure similar to that of the trench 4a, and a gate insulating film is formed on a bottom surface and a side surface in the trench. In addition, an inner region surrounded by the gate insulating film in the trench is filled with polysilicon having an impurity concentration of about 1×10.sup.20 cm.sup.−3, for example, to form a wiring path. Since having the upper surface covered with the insulating film 8, the wiring path is insulated and separated from the emitter electrode 9.

[0061] The trench routing wiring line 4d has a trench structure similar to that of the trench 4b, and a gate insulating film is formed on a bottom surface and a side surface in the trench. In addition, an inner region surrounded by the gate insulating film in the trench is filled with polysilicon having an impurity concentration of about 1×10.sup.20 cm.sup.−3, for example, to form a wiring path. Since having the upper surface covered with the insulating film 8, the wiring path is insulated and separated from the emitter electrode 9.

[0062] The surface layer on the second main surface (collector surface) of the n-type semiconductor substrate 30 is formed with a p-type (p.sup.+) collector region 2. In the present preferred embodiment, the p.sup.+-type collector region 2 has, for example, a thickness of about 0.5 μm and an impurity concentration of about 1×10.sup.18 cm.sup.−3.

[0063] In addition, in the present preferred embodiment, as shown with an example in FIG. 2, an n.sup.+-type buffer layer 1a for stopping a depletion layer is formed between the semiconductor substrate 30 and the p.sup.+-type collector region 2.

[0064] In the configuration shown in FIG. 2, the thickness from the upper surface (that is, the upper surface of the semiconductor substrate 30) in the p-type base region 3 to the lower surface (that is, the second main surface of the semiconductor substrate 30) in the p.sup.+-type collector region 2 is, for example, about 120 μm.

[0065] In addition, on the lower surface in the p.sup.+-type collector region 2, for example, a collector electrode 10 made of an aluminum-based material is provided. The p.sup.+-type collector region 2 and the collector electrode 10 are electrically connected. The collector electrode 10 is further connected to the collector terminal 80.

[0066] Incidentally, the operating temperature of the MG-IGBT and the threshold voltage have an inversely proportional relationship, and the threshold voltage at room temperature decreases by about 15% at a temperature of 125° C.

[0067] Since the threshold voltage varies in inverse proportion to the temperature, the threshold voltage of the main gate becomes lower during high-temperature operation than during room-temperature operation, which causes malfunction due to external noise voltage.

[0068] Thus, in the MG-IGBT according to the present preferred embodiment, gates having different threshold voltages are used as the main gate depending on the operating temperature of the MG-IGBT element 31. It should be noted that the operating temperature of the semiconductor device corresponds to the temperature of the loss occurrence starting point of the semiconductor device. The loss occurrence starting point of the semiconductor device refers to a temperature near the pn boundary, corresponds to the junction temperature (Tj) in the bipolar transistor because the pn junction maintaining the withstand voltage characteristic is the loss occurrence starting point, and corresponds to the channel temperature (Tc) in the MOSFET because the region maintaining the withstand voltage characteristic and having a channel formed by the gate signal is the loss occurrence starting point.

[0069] In the present preferred embodiment, since the impurity concentration of the p-type base region 3b corresponding to the second channel formation region is higher than the impurity concentration of the p-type base region 3a corresponding to the first channel formation region, the threshold voltage (gate voltage) for forming a channel in the second channel formation region is higher than the threshold voltage (gate voltage) for forming a channel in the first channel formation region.

[0070] As a specific operation, when the operating temperature of the MG-IGBT element 31 is lower than 75° C., switching control is performed with the gate electrode 7a being a low threshold voltage as a main gate, and the gate electrode 7 b is used as an auxiliary gate. Here, the auxiliary gate controls the internal carrier concentration of the MG-IGBT element 31. It should be noted that the gate electrode 7a is further connected to the gate terminal 70a. In addition, the gate electrode 7b is further connected to the gate terminal 70b.

[0071] When the gate electrode 7a is continuously switching-controlled as the main gate even when the operating temperature of the MG-IGBT element 31 is 75° C. or higher, it may cause a malfunction due to an external noise voltage.

[0072] Thus, when the operating temperature of the MG-IGBT element 31 is 75° C. or higher, the gate electrode 7b having a higher threshold voltage than the gate electrode 7a is switching-controlled as the main gate instead of the gate electrode 7a. Then, the gate electrode 7a is used as an auxiliary gate.

[0073] The reason why the main gate is selectively used as described above when the operating temperature of the MG-IGBT element 31 is 75° C. is that the multi-gate semiconductor device is generally used in a temperature range from room temperature (25° C.) to 125° C., and the operating temperature is divided at the intermediate temperature (75° C.) in the range.

[0074] The threshold voltage of the gate electrode 7b used as the main gate when the operating temperature of the MG-IGBT is 75° C. or higher is set to have a voltage difference of about 15% (that is, the threshold voltage of the gate electrode 7b is higher, by 10% or more, than the threshold voltage of the gate electrode 7a) as compared with the threshold voltage of the gate electrode 7a used as the main gate when the operating temperature of the MG-IGBT is lower than 75° C.

[0075] Since the threshold voltage at the temperature of 125° C. is about 15% lower than the threshold voltage at the room temperature of 25° C., the threshold voltage at the intermediate temperature (75° C.) is about several % lower than the threshold voltage at the room temperature (25° C.). Therefore, in consideration of a manufacturing error at the time of device manufacturing, by setting the threshold voltage of the gate electrode 7a and the threshold voltage of the gate electrode 7b to have a voltage difference of about 15%, the threshold voltage (that is, the threshold voltage decreased by about 5%) of the gate electrode 7b at the intermediate temperature (75° C.) is prevented from being equal to or less than the threshold voltage of the gate electrode 7a at room temperature (25° C.).

[0076] The main gate is selectively used depending on not only the above temperature condition but also the current value. When a rated current is flowed as a direct current at room temperature (25° C.), the temperature of the multi-gate semiconductor device reaches about 125° C. due to conduction loss, so that 125° C. can be set as the upper limit of the operating temperature. In actual application, a current is not flowed as a direct current, but a rated current is flowed with a pulse wave, and a temperature of the multi-gate semiconductor device reaches about 125° C. by heat generated from a sum of a conduction loss and a switching loss due to the pulse current. When a current of ½ of the rated current is flowed, the temperature of the multi-gate semiconductor device is about 75° C., so that the gate electrode 7a and the gate electrode 7b can be selectively used in consideration of the influence of the current.

[0077] FIG. 3 is a diagram for illustrating a method for driving the multi-gate semiconductor device according to the present preferred embodiment. In FIG. 3, together with a voltage V.sub.CE applied between the collector terminal 80 and the emitter terminal 90, a conduction period and a non-conduction period between the collector terminal 80 and the emitter terminal 90 (that is, a layer structure sandwiched between the collector terminal 80 and the emitter terminal 90) are shown.

[0078] A state at a low temperature (that is, the temperature of the multi-gate semiconductor device is lower than 75° C.) is defined as an α state. In addition, the condition that the turn-on switching current (current flowing when the multi-gate semiconductor device comes into the ON state being the conductive state) or the turn-off switching current (current flowing when the multi-gate semiconductor device comes into the OFF state being the non-conductive state) is less than ½ of the rated current A is defined as the β condition.

[0079] In this case, in the α state and the β condition, the gate electrode (first gate) having a lower threshold voltage is set as the main gate, and the gate electrode (second gate) having a higher threshold voltage is set as the auxiliary gate. Then, at the time of turn-on switching, the turn-on control signal is input from the auxiliary gate later by the “adjustment time TonL” than the time of turn-on switching (that is, temporally later), and at the time of turn-off switching, the turn-off control signal is input from the auxiliary gate earlier by the “adjustment time ToffL” than the time of turn-off switching (that is, temporally later). It should be noted that even when the β condition is not satisfied (that is, when only the α state is satisfied), a gate electrode (first gate) having a lower threshold voltage is set as the main gate, a gate electrode (second gate) having a higher threshold voltage is set as the auxiliary gate, a turn-on control signal can be input from the auxiliary gate later by the “adjustment time TonL” than the time of turn-on switching at the time of turn-on switching, and a turn-off control signal can be input from the auxiliary gate earlier by the “adjustment time ToffL” than the time of turn-off switching at the time of turn-off switching.

[0080] In order to reduce the loss at the time of the turn-on switching, it is desirable to simultaneously input the turn-on control signals of the main gate and the auxiliary gate without shifting the input timings. However, in this case, the surge current at the time of turn-on switching increases, and dI.sub.on/dt at the time of turn-on switching increases, which adversely affects EMI. Therefore, it is desirable to provide an appropriate “adjustment time TonL” in order to reduce dI.sub.on/dt.

[0081] In order to reduce the loss at the time of the turn-off switching, it is desirable to greatly shift the input timings of the turn-off control signals of the main gate and the auxiliary gate. However, in this case, the surge voltage at the time of the turn-off switching increases, and dV.sub.off/dt at the time of the turn-off switching increases, which adversely affects EMI. Therefore, in order to reduce dV.sub.off/dt, it is desirable to provide an appropriate “adjustment time ToffL” that is not too large.

[0082] On the other hand, when a gate electrode having a low threshold voltage at a high temperature is used as the main gate, malfunction is likely to occur when the threshold voltage decreases due to the influence of temperature, Thus, at the time of high temperature, the second gate having a threshold voltage equal to or higher than the threshold voltage of the first gate at the time of low temperature even at the time of high temperature is set as the main gate, and instead, the first gate that has been set as the main gate at the time of low temperature is switched to the auxiliary gate.

[0083] A state at a high temperature (that is, the temperature of the multi-gate semiconductor device is equal to or higher than 75° C.) is defined as the γ state. In addition, the condition that the turn-on switching current (current flowing when the multi-gate semiconductor device comes into the ON state) or the turn-off switching current (current flowing when the multi-gate semiconductor device comes into the OFF state) is equal to or larger than ½ of the rated current A is defined as the β condition.

[0084] In this case, in the γ state or the β condition, the gate electrode (first gate) having a lower threshold voltage is set as the auxiliary gate, and the gate electrode (second gate) having a higher threshold voltage is set as the main gate. Then, at the time of turn-on switching, the turn-on control signal is input from the auxiliary gate earlier by the “adjustment time TonH” than the time of turn-on switching (that is, temporally earlier), and at the time of turn-off switching, the turn-off control signal is input from the auxiliary gate later by the “adjustment time ToffH” than the time of turn-off switching (that is, temporally later).

[0085] The “adjustment time TonH” or the “adjustment time ToffH” needs to be appropriately selected in consideration of dI.sub.on/dt or dV.sub.off/dt so as not to adversely affect EMI.

[0086] Incidentally, in order to make the threshold voltage of the gate electrode 7b (second gate) higher than the threshold voltage of the gate electrode 7a (first gate), there is a method of making the impurity concentration of the p-type base region 3b higher than the impurity concentration of the p-type base region 3a, making the thickness of the gate insulating film 6b larger than the thickness of the gate insulating film 6a, making the dielectric constant of the gate insulating film 6b lower than the dielectric constant of the gate insulating film 6a, making the gate length of the gate electrode 7b (distance of the p-type base region 3b from the n.sup.4-type emitter layer 5b to the n-type base layer 1) larger than the gate length of the gate electrode 7a (distance of the p-type base region 3a from the n.sup.+-type emitter layer 5a to the n-type base layer 1), or the like.

[0087] In the MG-IGBT element 31 according to the present preferred embodiment, the threshold voltage of the gate electrode 7b (second gate) is made higher than the threshold voltage of the gate electrode 7a (first gate) by making the impurity concentration in the p-type base region 3b higher than the impurity concentration in the p-type base region 3a, but the threshold voltage of the gate electrode 7b (second gate) may be made higher than the threshold voltage of the gate electrode 7a (first gate) using (or combining) at least one of the methods listed above.

[0088] FIG. 4 is a cross-sectional view schematically showing another configuration example of the multi-gate semiconductor device according to the present preferred embodiment. In FIG. 4, the gate length of the gate electrode 7b is larger than the gate length of the gate electrode 7a.

[0089] As shown with an example in FIG. 4, the surface layer of the n-type base layer 1 is formed with a p-type base region 3c and a p-type base region 3d having an impurity concentration higher than the impurity concentration in the p-type base region 3c. The p-type base region 3c and the p-type base region 3d are arranged alternately with each other as shown with an example in FIG. 4.

[0090] The p-type base region 3c is formed with a trench 4a that penetrates the p-type base region 3c and further reaches the inside of the n-type base layer 1. Similarly, the p-type base region 3d is formed with a trench 4b that penetrates the p-type base region 3d and further reaches the inside of the n-type base layer 1.

[0091] The bottom surface and the side surface in the trench 4a are formed with a gate insulating film 6a. In addition, an inner region surrounded by the gate insulating film 6a in the trench 4a is filled with, for example, polysilicon having an impurity concentration of about 1×10.sup.20 cm.sup.−3, and a gate electrode 7a is formed.

[0092] Similarly, the bottom surface and the side surface in the trench 4b are formed with a gate insulating film 6b. In addition, an inner region surrounded by the gate insulating film 6b in the trench 4b is filled with, for example, polysilicon having an impurity concentration of about 1×10.sup.20 cm.sup.−3, and a gate electrode 7b is formed.

[0093] In addition, the mesa shape 14 (that is, the p-type base region sandwiched between the adjacent trenches) partitioned by the trench 4a and the trench 4b is arranged with a p-type base region 3c and a p-type base region 3d. These structures are repeatedly arranged with the p-type base region 3c, the trench 4a, the p-type base region 3c, the p-type base region 3d, the trench 4b, and the p-type base region 3d in this order along the X-axis positive direction in FIG. 4.

[0094] In addition, the surface layer in the p-type base region 3c is selectively formed with an n-type (n.sup.+) emitter layer 5a adjacent to a part of the side surface portion of the gate electrode 7a. In addition, the surface layer in the p-type base region 3d is selectively formed with an n-type (n.sup.+) emitter layer 5b adjacent to a part of the side surface portion of the gate electrode 7b.

[0095] Here, the mesa shape 14 in which the n.sup.+-type emitter layer 5a and the n.sup.+-type emitter layer 5b are formed is also referred to as a mesa 14a. In addition, the mesa shape 14 in which the n.sup.+-type emitter layer 5a and the n.sup.+-type emitter layer 5b are not formed is also referred to as a mesa 14b. The mesa 14a and the mesa 14b are alternately arranged in the X-axis positive direction in FIG. 4.

[0096] In FIG. 4, the gate length of the gate electrode 7b (that is, the distance 30d of the p-type base region 3d from the lower surface of the n.sup.+-type emitter layer 5b to the n-type base layer 1) is larger than the gate length of the gate electrode 7a (that is, the distance 30c of the p-type base region 3c from the lower surface of the n.sup.+-type emitter layer 5a to the n-type base layer 1).

[0097] The structure illustrated in FIG. 4 can also produce effects similar to those of the structures illustrated in FIGS. 1 to 3.

[0098] According to the multi-gate semiconductor device according to the present preferred embodiment, the resistance to the external noise voltage can be increased and the malfunction can be suppressed by switching and using the gate electrodes having different threshold voltages as the main gate according to the operating condition. In addition, the loss can be suppressed by minimizing the sacrifice of the ON-voltage.

Second Preferred Embodiment

[0099] A semiconductor device and a method for driving the semiconductor device according to the present preferred embodiment will be described. It should be noted that in the following description, the same components as those described in the preferred embodiment described above are denoted by the same reference numerals and illustrated, and the detailed description thereof will be appropriately omitted.

[0100] <Configuration of Semiconductor Device>

[0101] In the present preferred embodiment, an MG-IGBT having three or more gates will be described as an example of a multi-gate semiconductor device having three or more gates.

[0102] FIG. 5 is a cross-sectional view schematically showing a configuration example of the multi-gate semiconductor device according to the present preferred embodiment. In the example shown in FIG. 5, the multi-gate semiconductor device includes three gates.

[0103] As shown with an example in FIG. 5, the surface layer on the first main surface in the n-type base layer 1 is formed with a p-type base region 3e, a p-type base region 3f having an impurity concentration higher than the impurity concentration in the p-type base region 3e, and a p-type base region 3g having an impurity concentration equal to or higher than the impurity concentration in the p-type base region 3e and equal to or lower than the impurity concentration in the p-type base region 3f.

[0104] The p-type base region 3e is formed with a trench 4a that penetrates the p-type base region 3e and further reaches the inside of the n-type base layer 1. Similarly, the p-type base region 3f is formed with a trench 4b that penetrates the p-type base region 3f and further reaches the inside of the n-type base layer 1. Similarly, the p-type base region 3g is formed with a trench 4f that penetrates the p-type base region 3g and further reaches the inside of the n-type base layer 1.

[0105] The bottom surface and the side surface in the trench 4a are formed with a gate insulating film 6a. In addition, an inner region surrounded by the gate insulating film 6a in the trench 4a is filled with, for example, polysilicon having an impurity concentration of about 1×10.sup.20 cm.sup.−3, and a gate electrode 7a is formed. The gate electrode 7a is further connected to the gate terminal 70a.

[0106] Similarly, the bottom surface and the side surface in the trench 4b are formed with a gate insulating film 6b. In addition, an inner region surrounded by the gate insulating film 6b in the trench 4b is filled with, for example, polysilicon having an impurity concentration of about 1×10.sup.20 cm.sup.−3, and a gate electrode 7b is formed. The gate electrode 7b is further connected to the gate terminal 70b.

[0107] Similarly, the bottom surface and the side surface in the trench 4f are formed with a gate insulating film 6c. In addition, an inner region surrounded by the gate insulating film 6c in the trench 4f is filled with, for example, polysilicon having an impurity concentration of about 1×10.sup.20 cm.sup.3, and a gate electrode 7c is formed. The gate electrode 7c is further connected to the gate terminal 70c.

[0108] In addition, the mesa shape 15 (that is, the p-type base region sandwiched between the adjacent trenches) partitioned by the trench 4a, the trench 4b, and the trench 4f is arranged with a p-type base region 3e, a p-type base region 3fe, and a p-type base region 3g. These structures are repeatedly arranged with the p-type base region 3e, the trench 4a, the p-type base region 3e, the p-type base region 3f, the trench 4b, the p-type base region 3f, the p-type base region 3e, the trench 4a, the p-type base region 3e, the p-type base region 3g, the trench 4f, and the p-type base region 3g in this order along the X-axis positive direction in FIG. 5.

[0109] In addition, the surface layer in the p-type base region 3e is selectively formed with an n-type (n.sup.+) emitter layer 5e adjacent to a part of the side surface portion of the gate electrode 7a. In addition, the surface layer in the p-type base region 3f is selectively formed with an n-type (n.sup.+) emitter layer 5f adjacent to a part of the side surface portion of the gate electrode 7b. In addition, the surface layer in the p-type base region 3g is selectively formed with an n-type (n.sup.+) emitter layer 5g adjacent to a part of the side surface portion of the gate electrode 7c.

[0110] Here, the mesa shape 15 in which the n.sup.+-type emitter layer 5e and the n.sup.+-type emitter layer 5f or the n.sup.+-type emitter layer 5e and the n.sup.+-type emitter layer 5g are formed is also referred to as a mesa 15a. In addition, the mesa shape 15 in which none of the n.sup.+-type emitter layer 5e and the n.sup.+-type emitter layer 5f or the n.sup.+-type emitter layer Se and the n.sup.+-type emitter layer 5g is formed is also referred to as a mesa 15b. The mesa 15a and the mesa 15b are alternately arranged in the X-axis positive direction in FIG. 5.

[0111] The p-type base region 3e facing the gate electrode 7a in the mesa 15a functions as a first channel formation region. In addition, the p-type base region 3f facing the gate electrode 7b in the mesa 15a functions as a second channel formation region. In addition, the p-type base region 3g facing the gate electrode 7c in the mesa 15a functions as a third channel formation region.

[0112] The upper surface of the n-type base layer 1 is partially formed with an insulating film 8. In addition, an emitter electrode 9 is formed to cover the insulating film 8 and the upper surface (that is, a part of the upper surface of the mesa 15a) of the n-type base layer 1 exposed without being covered with the insulating film 8. The emitter electrode 9 is further connected to the emitter terminal 90.

[0113] On the upper surface of the mesa 15a, the p-type base region 3e, the p-type base region 3f, the p-type base region 3g, the n.sup.+-type emitter layer 5e, the n.sup.+-type emitter layer 5f, and the n.sup.+-type emitter layer 5g are electrically connected to the emitter electrode 9. On the other hand, since covered with the insulating film 8, the upper surfaces of the trench 4a, the trench 4b, and the mesa 15b are insulated and separated from the emitter electrode 9. However, a small area of the upper surface of the mesa 15b is connected to the emitter electrode 9 and has contact resistance (not shown here).

[0114] Similarly to the case illustrated in FIG. 1, on the upper surface of the n-type base layer 1, a plurality of respective gate pads insulated and separated from the emitter electrode 9 are disposed to be connected to the corresponding gate terminal 70a, gate terminal 70b, and gate terminal 70c.

[0115] Each of the gate pads is made of an aluminum-based material. Then, each gate pad is electrically connected to the corresponding gate electrode through the trench routing wiring line.

[0116] Each trench routing wiring line has a trench structure similar to the trench 4a, the trench 4b, or the trench 4f, and the bottom surface and the side surface in the trench are formed with a gate insulating film. In addition, an inner region surrounded by the gate insulating film in the trench is filled with polysilicon having an impurity concentration of about 1×10.sup.20 cm.sup.−3, for example, to form a wiring path. Since having the upper surface covered with the insulating film 8, the wiring path is insulated and separated from the emitter electrode 9.

[0117] In the MG-IGBT according to the present preferred embodiment, the impurity concentration of the p-type base region 3f is higher than the impurity concentration of the p-type base region 3e. The impurity concentration of the p-type base region 3g is equal to or higher than the impurity concentration of the p-type base region 3e and equal to or lower than the impurity concentration of the p-type base region 3f.

[0118] Therefore, regarding the threshold voltage magnitude, the threshold voltage of the gate electrode 7a≤the threshold voltage of the gate electrode 7c≤the threshold voltage of the gate electrode 7b.

[0119] Therefore, when the turn-on control signals (voltages) having the same magnitude are input, the channel is formed in the order of the p-type base region 3e facing the gate electrode 7a (first gate), the p-type base region 3g facing the gate electrode 7c (third gate d the p-type base region 3f facing the gate electrode 7b (second gate). In addition, when the turn-off control signal (voltage) having the same magnitude is input, the channel disappears in the order of the p-type base region 3f facing the gate electrode 7b, the p-type base region 3g facing the gate electrode 7c, and the p-type base region 3e facing the gate electrode 7a.

[0120] When the third gate is controlled according to the purpose, control of the switching waveform more precise than a case of control with only two gates of the first gate and the second gate (specifically, precise control of dI.sub.on/dt or dV.sub.off/dt) is made possible, and it is possible to secure the likelihood of waveform adjustment. Thus, the third gate is used as an auxiliary gate under any condition.

[0121] In other words, α state at a low temperature (that is, the temperature of the multi-gate semiconductor device is lower than 75° C.) is defined as an α state. In addition, the condition that the turn-on switching current (current flowing when the multi-gate semiconductor device comes into the ON state) or the turn-off switching current (current flowing when the multi-gate semiconductor device comes into the OFF state) is less than ½ of the rated current A is defined as the β condition.

[0122] In this case, in the α state and the β condition, the gate electrode (first gate) having a lower threshold voltage is set as the main gate, and the gate electrode (second gate and third gate) having a higher threshold voltage is set as the auxiliary gate. Then, at the time of turn-on switching, the turn-on control signal is input from the auxiliary gate later by the “adjustment time TonL” than the time of turn-on switching (that is, temporally later), and at the time of turn-off switching, the turn-off control signal is input from the auxiliary gate earlier by the “adjustment time ToffL” than the time of turn-off switching (that is, temporally later). It should be noted that even when the β condition is not satisfied (that is, when only the α state is satisfied), a gate electrode (first gate) having a lower threshold voltage is set as the main gate, a gate electrode (second gate and third gate) having a higher threshold voltage is set as the auxiliary gate, a turn-on control signal can be input from the auxiliary gate later by the “adjustment time TonL” than the time of turn-on switching at the time of turn-on switching, and a turn-off control signal can be input from the auxiliary gate earlier by the “adjustment time ToffL” than the time of turn-off switching at the time of turn-off switching.

[0123] A state at a high temperature (that is, the temperature of the multi-gate semiconductor device is equal to or higher than 75° C.) is defined as the γ state. In addition, the condition that the turn-on switching current (current flowing when the multi-gate semiconductor device comes into the ON state) or the turn-off switching current (current flowing when the multi-gate semiconductor device comes into the OFF state) is equal to or larger than ½ of the rated current A is defined as the δ condition.

[0124] In this case, in the γ state or the β condition, the gate electrode (first gate and third gate) having a lower threshold voltage is set as the auxiliary gate, and the gate electrode (second gate) having a higher threshold voltage is set as the main gate. Then, at the time of turn-on switching, the turn-on control signal is input from the auxiliary gate earlier by the “adjustment time TonH” than the time of turn-on switching (that is, temporally earlier), and at the time of turn-off switching, the turn-off control signal is input from the auxiliary gate later by the “adjustment time ToffH” than the time of turn-off switching (that is, temporally later).

[0125] Although the third gate is used as the auxiliary gate in the above example, if the input timings of the turn-on control signals of the main gate and the third gate are substantially at the same time without shifting, EMI is sacrificed, but a loss at the time of turn-on switching can be reduced. In addition, if the input timings of the turn-off control signals of the main gate and the third gate are substantially at the same time without shifting, EMI is sacrificed, but a loss at the time of turn-off switching can be reduced. Therefore, it is desirable to adjust the input timing of the third gate in accordance with the operating condition of the apparatus to be applied.

Third Preferred Embodiment

[0126] A semiconductor device and a method for driving the semiconductor device according to the present preferred embodiment will be described. It should be noted that in the following description, the same components as those described in the preferred embodiment described above are denoted by the same reference numerals and illustrated, and the detailed description thereof will be appropriately omitted.

[0127] <Configuration of Semiconductor Device>

[0128] In the present preferred embodiment, an MG-IGBT will be described as an example of a multi-gate semiconductor device in which an auxiliary gate is provided on a second main surface (collector surface) of the structure illustrated in FIG. 2.

[0129] FIG. 6 is a cross-sectional view schematically showing a configuration example of the multi-gate semiconductor device according to the present preferred embodiment.

[0130] As shown with an example in FIG. 6, the surface layer on the first main surface of the n-type base layer 1 is formed with a p-type base region 3a, a p-type base region 3b, a trench 4a, a trench 4b, a gate insulating film 6a, a gate insulating film 6b, a gate electrode 7a, a gate electrode 7b, an n.sup.+-type emitter layer 5a, and an n.sup.+-type emitter layer 5b. It should be noted that the gate electrode 7a is further connected to the gate terminal 70a. In addition, the gate electrode 7b is further connected to the gate terminal 70b. The upper surface of the n-type base layer 1 is formed with an insulating film 8 and an emitter electrode 9. The emitter electrode 9 is further connected to the emitter terminal 90.

[0131] The surface layer on the second main surface (collector surface) of the n-type base layer 1 is formed with a p-type (p.sup.+) collector region 2. It should be noted that an n.sup.+-type buffer layer 1a for suppressing extension of a depletion layer may be provided between the p.sup.+-type collector region 2 and the n-type base layer 1.

[0132] The p.sup.+-type collector region 2 is selectively formed with a trench 21 that penetrates the p.sup.+-type collector region 2 and further reaches the inside of the n-type base layer 1.

[0133] The bottom surface and the side surface in the trench 21 are formed with a gate insulating film 16. In addition, an inner region surrounded by the gate insulating film 16 in the trench 21 is filled with, for example, polysilicon having an impurity concentration of about 1×10.sup.20 cm.sup.−3, and a gate electrode 17 is formed. The gate electrode 17 is further connected to the gate terminal 70d.

[0134] The p.sup.+-type collector region 2 sandwiched between the adjacent trenches 21 is also referred to as a mesa shape 18.

[0135] In addition, the surface layer in the p+-type collector region 2 is selectively formed with an n-type (n.sup.+) collector layer 19 adjacent to a part of the side surface portion of the gate electrode 17.

[0136] Here, the mesa shape 18 in which the n.sup.+-type collector layer 19 is formed is also referred to as a mesa 18a. In addition, the mesa shape 18 in which the n.sup.+-type collector layer 19 is not formed is also referred to as a mesa 18h. The mesa 18a and the mesa 18b are alternately arranged in the X-axis positive direction in FIG. 6.

[0137] The p.sup.+-type collector region 2 facing the gate electrode 17 (fourth gate) in the mesa 18a functions as a fourth channel formation region.

[0138] The lower surface of the n-type base layer 1 is partially formed with an insulating film 20. In addition, a collector electrode 10 is formed to cover the insulating film 20 and the lower surface (that is, a part of the lower surface of the mesa 18a) of the n-type base layer 1 exposed without being covered with the insulating film 20. The collector electrode 10 is further connected to the collector terminal 80.

[0139] On the lower surface of the mesa 18a, the p.sup.+-type collector region 2 and the n.sup.+-type collector layer 19 are electrically connected to the collector electrode 10.

[0140] On the other hand, since covered with the insulating film 20, the lower surfaces of the trench 21 and the mesa 18b are insulated and separated from the collector electrode 10.

[0141] In addition, on the lower surface of the n-type base layer 1, a gate pad insulated and separated from the collector electrode 10 is disposed to be connected to the gate terminal 70d.

[0142] The gate pad is made of an aluminum-based material. Then, the gate pad is electrically connected to the corresponding gate electrode 17 through the trench routing wiring line.

[0143] In the MG-IGBT configured as described above, the gate electrode 17 (fourth gate) is used as an auxiliary gate under any condition.

[0144] By forming a channel in the p+-type collector region 2 facing the gate electrode 17 (fourth gate), an electrical path from the n-type base layer 1 to the collector electrode 10 in the MG-IGBT is formed.

[0145] Therefore, carriers in the MG-IGBT can be adjusted not only from the first main surface (emitter surface) side of the n-type base layer 1 but also from the second main surface (collector surface) side of the n-type base layer 1.

[0146] Here, adjusting carriers inside the MG-IGBT from the first main surface (emitter surface) side of the n-type base layer 1 is effective for controlling carriers present on the first main surface side. In addition, adjusting carriers inside the MG-IGBT from the second main surface (collector surface) side of the n-type base layer 1 is effective for controlling carriers present on the second main surface side.

[0147] Therefore, by using the gate electrode 17 (fourth gate) as an auxiliary gate, it is possible to perform precise control with likelihood. That is, since the auxiliary gate on the second main surface (collector surface) is provided in addition to the auxiliary gate on the first main surface (emitter surface), the carrier density accumulated inside the IGBT can be controlled also from the second main surface (collector surface) side. As a result, the control time of the carrier density can be shortened, and the accuracy of the control can be improved, which is effective to reduce the loss or improve the accuracy of the waveform control.

[0148] It should be noted that in FIG. 6, the structure on the first main surface (emitter surface) is the structure shown in FIG. 2, but instead of the structure, the structure shown in FIG. 4 may be applied or the structure shown in FIG. 5 may be applied.

Fourth Preferred Embodiment

[0149] A power conversion apparatus and a method for manufacturing the power conversion apparatus according to the present preferred embodiment will be described. In the following description, the same components as those described in the preferred embodiments described above are denoted by the same reference numerals and illustrated, and the detailed description thereof will be appropriately omitted.

[0150] <Configuration of Power Conversion Apparatus>

[0151] The present preferred embodiment is obtained by applying the semiconductor device according to the above-described preferred embodiments to a power conversion apparatus. The power conversion apparatus to be applied is not limited to one for a specific use, but in the following, a case where the power conversion apparatus is applied to a three-phase inverter will be described.

[0152] FIG. 7 is a diagram conceptually showing an example of the configuration of a power conversion system including the power conversion apparatus according to the present preferred embodiment.

[0153] As shown with an example in FIG. 7, the power conversion system includes a power supply 2100, a power conversion apparatus 2200, and a load 2300. The power supply 2100 is a DC power supply, and supplies DC power to the power conversion apparatus 2200. The power supply 2100 can include various things, such as a DC system, a solar cell, a storage battery, or the like. In addition, the power supply 2100 can include a rectifier circuit connected to an AC system, an AC-DC converter, or the like. In addition, the power supply 2100 may include a DC-DC converter for converting DC power output from the DC system into predetermined power.

[0154] The power conversion apparatus 2200 is a three-phase inverter connected between the power supply 2100 and the load 2300. The power conversion apparatus 2200 converts the DC power supplied from the power supply 2100 into AC power, and further supplies the AC power to the load 2300.

[0155] In addition, as shown with an example in FIG. 7, the power conversion apparatus 2200 includes a conversion circuit 2201 for converting DC power into AC power to output the converted power, a drive circuit 2202 for outputting a drive signal for driving each switching element of the conversion circuit 2201, and a control circuit 2203 for outputting a control signal for controlling the drive circuit 2202 to the drive circuit 2202.

[0156] The load 2300 is a three-phase electric motor driven by AC power supplied from the power conversion apparatus 2200. It should be noted that the load 2300 is not limited to a specific use, and is an electric motor to be mounted on various electric apparatuses, and is used as, for example, a hybrid vehicle, an electric vehicle, a railway vehicle, an elevator, or an electric motor for an air conditioner.

[0157] Hereinafter, details of the power conversion apparatus 2200 will be described. The conversion circuit 2201 includes a switching element and a reflux diode (not shown here). Then, the switching element performs switching operation to convert the DC power supplied from the power supply 2100 into AC power, and further supplies the AC power to the load 2300.

[0158] There are various specific circuit configurations of the conversion circuit 2201, and the conversion circuit 2201 according to the present preferred embodiment is a two-level three-phase full bridge circuit and includes six switching elements and six reflux diodes connected antiparallel to the respective switching elements.

[0159] The semiconductor device according to any one of the above-described preferred embodiments is applied to at least one of each switching element and each reflux diode in the conversion circuit 2201. The six switching elements are connected in series for every two switching elements to constitute upper and lower arms, and the respective upper and lower arms constitute each phase (that is, U phase, V phase, and W phase) of the full bridge circuit. Then, the output terminals of the respective upper and lower arms (that is, the three output terminals of the conversion circuit 2201) are connected to the load 2300.

[0160] The drive circuit 2202 generates drive signals for driving the switching elements of the conversion circuit 2201, and further supplies the drive signals to the control electrodes of the switching elements of the conversion circuit 2201. Specifically, based on a control signal output from a control circuit 2203 described below, a drive signal to turn the switching element into the ON state and a drive signal to turn the switching element into the OFF state are output to the control electrodes of the respective switching elements.

[0161] When the switching element is maintained in the ON state, the drive signal is a voltage signal equal to or more than the threshold voltage of the switching element (that is, ON signal), and when the switching element is maintained in the OFF state, the drive signal is a voltage signal equal to or less than the threshold voltage of the switching element (that is, OFF signal).

[0162] The control circuit 2203 controls the switching elements of the conversion circuit 2201 so that desired power is supplied to the load 2300. Specifically, based on the power to be supplied to the load 2300, the time required for each switching element of the conversion circuit 2201 to be in the ON state (that is, ON time) is calculated. For example, the PWM control for modulating the ON time of the switching element according to the voltage to be output can control the conversion circuit 2201.

[0163] Then, the control circuit 2203 outputs a control instruction (that is, control signal) to the drive circuit 2202 so that, at each time point, the ON signal is output to the switching element to be turned on and the OFF signal is output to the switching element to be turned off. The drive circuit 2202 outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element based on the control signal.

[0164] In the power conversion apparatus 2200 according to the present preferred embodiment, since the semiconductor device according to any one of the preferred embodiments described above is applied as the switching element of the conversion circuit 2201, it is possible to stabilize the ON-resistance after going through the energization cycle.

[0165] It should be noted that in the present preferred embodiment, an example in which the semiconductor device according to any one of the preferred embodiments described above is applied to a two-level three-phase inverter has been described, but the application example is not limited to this. The semiconductor device according to any of the above-described preferred embodiments can be applied to various power conversion apparatuses.

[0166] In addition, although a two-level power conversion apparatus has been described in the present preferred embodiment, the semiconductor device according to any one of the above-described preferred embodiments may be applied to a three-level or multi-level power conversion apparatus. In addition, when power is supplied to a single-phase load, the semiconductor device according to any one of the preferred embodiments described above may be applied to a single-phase inverter.

[0167] In addition, when power is supplied to a DC load or the like, the semiconductor device according to any one of the preferred embodiments described above can also be applied to the DC-DC converter or the AC-DC converter.

[0168] In addition, the power conversion apparatus to which the semiconductor device according to any one of the above-described preferred embodiments is applied is not limited to the case where the load described above is an electric motor, and can also be used as a power supply apparatus for, for example, an electric discharge machine, a laser beam machine, an induction heating cooker, or a noncontact power feeding system. In addition, the power conversion apparatus to which the semiconductor device according to any one of the above-described preferred embodiments is applied can also be used as a power conditioner in a solar power generation system, a power storage system, or the like.

[0169] <Method for Manufacturing Power Conversion Apparatus>

[0170] Next, a method for manufacturing the power conversion apparatus according to the present preferred embodiment will be described.

[0171] First, a semiconductor device is manufactured by the manufacturing method described in the preferred embodiments described above. Then, the conversion circuit 2201 including the semiconductor device is provided as a configuration of the power conversion apparatus. The conversion circuit 2201 is a circuit for converting and outputting input power.

[0172] Then, a drive circuit 2202 is provided as a configuration of the power conversion apparatus. The drive circuit 2202 is a circuit for outputting a drive signal for driving the semiconductor device to the semiconductor device. Then, a control circuit 2203 is provided as a configuration of the power conversion apparatus. The control circuit 2203 is a circuit for outputting a control signal for controlling the drive circuit 2202 to the drive circuit 2202.

[0173] The semiconductor switching element used in the preferred embodiments described above is not limited to a switching element made of a silicon (Si) semiconductor, and for example, the semiconductor switching element may be made of a non-Si semiconductor material having a wider band gap than a Si semiconductor.

[0174] Examples of the wide band gap semiconductor being a non-Si semiconductor material include silicon carbide, a gallium nitride-based material, and diamond.

[0175] A switching element made of a wide band gap semiconductor can be used even in a high voltage region where unipolar operation is difficult with a Si semiconductor, and a switching loss generated at the time of switching operation can be greatly reduced. Therefore, the power loss can be greatly reduced.

[0176] In addition, a switching element made of a wide band gap semiconductor has a small power loss and high heat resistance. Therefore, when a power module including a cooling unit is configured, the heat dissipation fin of the heat sink can be reduced in size, so that the semiconductor module can be further reduced in size.

[0177] In addition, a switching element made of a wide bandgap semiconductor is suitable for high-frequency switching operation. Therefore, when the switching element made of a wide bandgap semiconductor is applied to a converter circuit in which there is a large demand for higher frequency, a reactor, a capacitor, or the like to be connected to the converter circuit can also be reduced in size by increasing the switching frequency. Therefore, the semiconductor switching element according to the preferred embodiments described above can obtain similar effects even when the semiconductor switching element is a switching element made of a wide-gap semiconductor such as silicon carbide.

Effects Produced by Preferred Embodiments Described Above

[0178] Next, examples of effects produced by the above-described preferred embodiments will be shown. It should be noted that in the following description, the effects are described based on the specific configuration exemplified in the above-described preferred embodiments, but in the scope where the same effects are produced, the configuration may be replaced with other specific configurations exemplified in the specification of the present application. That is, in the following description, for convenience, only one of the associated specific configurations may be described as a representative, but the specific configuration described as a representative may be replaced with associated another specific configuration.

[0179] In addition, the replacement may be performed across a plurality of preferred embodiments. That is, the case may be used where the same effects are produced by combining the respective configurations exemplified in different preferred embodiments.

[0180] According to the preferred embodiments described above, a semiconductor device includes a layer structure, and a first main electrode and a second main electrode conductive through the layer structure. Here, the first main electrode corresponds to, for example, the emitter electrode 9. In addition, the second main electrode corresponds to, for example, the collector electrode 10. The layer structure includes a first semiconductor layer of a first conductivity type, a first semiconductor region of a second conductivity type, a second semiconductor region of a second conductivity type, a second semiconductor layer of a first conductivity type, a first gate insulating film, a second gate insulating film, a first gate electrode, and a second gate electrode. Here, the first semiconductor layer of the first conductivity type corresponds to, for example, at least one of the n-type base layer 1, the n-type semiconductor substrate 30, or the like. In addition, the first semiconductor region of the second conductivity type corresponds to, for example, at least one of the p-type base region 3a, the p-type base region 3c, the p-type base region 3e, and the like. In addition, the second semiconductor region of the second conductivity type corresponds to, for example, at least one of the p-type base region 3b, the p-type base region 3d, the p-type base region 3f, and the like. In addition, the second semiconductor layer of the first conductivity type corresponds to, for example, at least one of an n.sup.+-type emitter layer 5a, an n.sup.+-type emitter layer 5b, an n.sup.+-type emitter layer 5c, an n.sup.+-type emitter layer 5d, an n.sup.+-type emitter layer 5e, an n.sup.+-type emitter layer 5f, an n.sup.+-type emitter layer 5g, and the like. In addition, the first gate insulating film corresponds to, for example, the gate insulating film 6a. In addition, the second gate insulating film corresponds to, for example, the gate insulating film 6b. In addition, the first gate electrode corresponds to, for example, the gate electrode 7a. In addition, the second gate electrode corresponds to, for example, the gate electrode 7b. The n-type base layer 1 has a first surface and a second surface opposite to the first surface. The p-type base region 3a is partially provided in the surface layer on the first surface. The p-type base region 3b is partially provided in the surface layer on the first surface. The n.sup.+-type emitter layer 5a is partially provided in the surface layer in the p-type base region 3a. The n.sup.+-type emitter layer 5b is partially provided in the surface layer in the p-type base region 3b. The gate insulating film 6a is provided in contact with the p-type base region 3a (or, the p-type base region 3e) sandwiched between the n-type base layer 1 and the n.sup.+-type emitter layer 5a (or, the n.sup.+-type emitter layer 5e). The gate insulating film 6b is provided in contact with the p-type base region 3b (or, the p-type base region 30 sandwiched between the n-type base layer 1 and the n.sup.+-type emitter layer 5b (or, the n.sup.+-type emitter layer 50. The gate electrode 7a is a gate electrode provided in contact with the gate insulating film 6a. The gate electrode 7b is a gate electrode provided in contact with the gate insulating film 6b. Applying a voltage to the gate electrode 7a or the gate electrode 7b makes it possible to switch between an ON state in which the emitter electrode 9 and the collector electrode 10 are conducting through the layer structure and an OFF state in which the emitter electrode 9 and the collector electrode 10 are not conducting through the layer structure. The threshold voltage of the gate electrode 7b is higher than the threshold voltage of the gate electrode 7a. Here, α state in which the temperature of the layer structure is lower than the threshold temperature is defined as an α state. In addition, a condition that the switching current, which is a current value at the time of the switching operation for switching to the ON state or the OFF state, is less than the threshold current is defined as a β condition. In addition, α state in which the temperature of the layer structure is equal to or higher than the threshold temperature is defined as a γ state. In addition, a condition that the switching current is equal to or larger than the threshold current is defined as a δ condition. In the α state and the β condition, the switching operation is performed using the gate electrode 7a. In the γ state or the δ condition, the switching operation is performed using the gate electrode 7b.

[0181] According to this configuration, even when the threshold voltage of the gate electrode fluctuates with the change in the operating temperature, occurrence of malfunction of the semiconductor device can be effectively suppressed by selectively using a plurality of gate electrodes having different threshold voltages according to the operating temperature.

[0182] It should be noted that even when another configuration exemplified in the specification of the present application is appropriately added to the above configuration, that is, even when another configuration in the specification of the present application not referred to as the above configuration is appropriately added, a similar effect can be produced.

[0183] It should be noted that by performing control so that the voltage value applied to the main gate and the voltage value applied to the auxiliary gate are different from each other, it is also possible to produce the same effects as described above, but a circuit or the like for controlling a plurality of gate voltages is separately required, and the manufacturing cost also increases.

[0184] In addition, according to the preferred embodiments described above, the threshold temperature is 75° C. According to this configuration, even when the operating temperature fluctuates in the temperature range of room temperature (25° C.) to 125° C., occurrence of malfunction of the semiconductor device can be effectively suppressed by selectively using the plurality of gate electrodes having different threshold voltages according to the operating temperature.

[0185] In addition, according to the preferred embodiments described above, the threshold current is ½ of the rated current. According to this configuration, even when the operating temperature fluctuates in the temperature range of room temperature (25° C.) to 125° C. due to the influence of the rated current, occurrence of malfunction of the semiconductor device can be effectively suppressed by selectively using the plurality of gate electrodes having different threshold voltages according to the operating temperature. In addition, according to the preferred embodiments described above, the semiconductor device includes the third semiconductor region of the second conductivity type, the third semiconductor layer of the first conductivity type, the third gate insulating film, and the third gate electrode. Here, the third semiconductor region corresponds to, for example, the p.sup.+-type collector region 2. In addition, the third semiconductor layer corresponds to, for example, the n.sup.+-type collector layer 19. In addition, the third gate insulating film corresponds to, for example, the gate insulating film 16. In addition, the third gate electrode corresponds to, for example, the gate electrode 17. The p.sup.+-type collector region 2 is partially provided in the surface layer on the second surface. The n.sup.+-type collector layer 19 is partially provided in the surface layer in the p.sup.+-type collector region 2. The gate insulating film 16 is provided in contact with the p.sup.+-type collector region 2 sandwiched between the n-type base layer 1 and the n.sup.+-type collector layer 19. The gate electrode 17 is a gate electrode formed in contact with the gate insulating film 16. According to this configuration, by combining not only the plurality of gates on the first main surface but also the gates on the second main surface, the carrier density accumulated inside the IGBT can be controlled also from the second main surface (collector surface) side. As a result, the control time of the carrier density can be shortened, and the accuracy of the control can be improved, which is effective to reduce the loss or improve the accuracy of the waveform control.

[0186] In addition, according to the preferred embodiments described above, the impurity concentration of the p-type base region 3b is higher than the impurity concentration of the p-type base region 3a. According to this configuration, the threshold voltage of the gate electrode 7b (second gate) can be made higher than the threshold voltage of the gate electrode 7a (first gate).

[0187] In addition, according to the preferred embodiments described above, the thickness of the gate insulating film 6b is larger than the thickness of the gate insulating film 6a. According to this configuration, the threshold voltage of the gate electrode 7b (second gate) can be made higher than the threshold voltage of the gate electrode 7a (first gate).

[0188] In addition, according to the preferred embodiments described above, the dielectric constant of the gate insulating film 6b serving as the channel is lower than the dielectric constant of the gate insulating film 6a serving as the channel. According to this configuration, the threshold voltage of the gate electrode 7b (second gate) can be made higher than the threshold voltage of the gate electrode 7a (first gate).

[0189] In addition, according to the preferred embodiments described above, the gate length of the gate electrode 7b is larger than the gate length of the gate electrode 7a. According to this configuration, the threshold voltage of the gate electrode 7b (second gate) can be made higher than the threshold voltage of the gate electrode 7a (first gate).

[0190] In addition, according to the preferred embodiments described above, the threshold voltage of the gate electrode 7b is higher than the threshold voltage of the gate electrode 7a by 10% or more. According to this configuration, even when the threshold voltage fluctuates with a change in the operating temperature, it is possible to prevent the threshold voltage from becoming equal to or lower than the threshold voltage of the gate electrode at a low temperature. Therefore, it is possible to suppress occurrence of malfunction caused by the external noise voltage.

[0191] In addition, according to the preferred embodiments described above, the semiconductor device includes the fourth semiconductor region of the second conductivity type, the fourth gate insulating film, and the fourth gate electrode. Here, the fourth semiconductor region corresponds to, for example, the p-type base region 3g. In addition, the fourth gate insulating film corresponds to, for example, the gate insulating film 6c. In addition, the fourth gate electrode corresponds to, for example, the gate electrode 7c. The p-type base region 3g is partially provided in the surface layer on the first surface. The n+-type emitter layer 5g is also partially provided in the surface layer in the p-type base region 3g. The gate insulating film 6c is provided in contact with the p-type base region 3g sandwiched between the n-type base layer 1 and the n.sup.+-type emitter layer 5g. The gate electrode 7c is a gate electrode provided in contact with the gate insulating film 6c. The threshold voltage of the gate electrode 7c is equal to or higher than the threshold voltage of the gate electrode 7a. According to this configuration, it is possible to precisely control the switching waveform (specifically, precise control of dI.sub.on/dt or dV.sub.off/dt) and to secure the likelihood of waveform adjustment.

[0192] In addition, according to the preferred embodiments described above, the threshold voltage of the gate electrode 7c is equal to or lower than the threshold voltage of the gate electrode 7b. According to this configuration, it is possible to precisely control the switching waveform (specifically, precise control of dI.sub.on/dt or dV.sub.off/dt) and to secure the likelihood of waveform adjustment.

[0193] In addition, according to the preferred embodiments described above, after the switching operation for switching to the ON state is performed, the voltage applied to the gate electrode not used for the switching operation is switched. According to such a configuration, it is possible to suppress an increase in dI.sub.on/dt during the turn-on switching due to the surge current during the turn-on switching, and thus, it is possible to reduce the turn-on loss.

[0194] In addition, according to the preferred embodiments described above, the power conversion apparatus includes the conversion circuit 2201 that includes the semiconductor device and converts and outputs the input power, the drive circuit 2202 that outputs a drive signal for driving the semiconductor device to the semiconductor device, and the control circuit 2203 that outputs a control signal for controlling the drive circuit 2202 to the drive circuit 2202. According to this configuration, even when the threshold voltage of the gate electrode fluctuates with the change in the operating temperature, occurrence of malfunction of the semiconductor device and further malfunction of the power conversion apparatus can be effectively suppressed by selectively using a plurality of gate electrodes having different threshold voltages according to the operating temperature.

[0195] According to the preferred embodiments described above, in a method for driving a semiconductor device, the semiconductor device includes a layer structure, and an emitter electrode 9 and a collector electrode 10 that are conductive through the layer structure. The layer structure includes an n-type base layer 1 having a first surface and a second surface opposite the first surface, a p-type base region 3a partially provided in a surface layer on the first surface, a p-type base region 3b partially provided in a surface layer on the first surface, an n.sup.+-type emitter layer 5a partially provided in a surface layer in the p-type base region 3a and in a surface layer in the p-type base region 3b, a gate insulating film 6a provided in contact with the p-type base region 3a sandwiched between the n-type base layer 1 and the second semiconductor layer, a gate insulating film 6b provided in contact with the p-type base region 3b sandwiched between the n-type base layer 1 and the second semiconductor layer, a gate electrode 7a being a gate electrode provided in contact with the gate insulating film 6a, and a gate electrode 7b being a gate electrode provided in contact with the gate insulating film 6b. Then, applying a voltage to the gate electrode 7a or the gate electrode 7b makes it possible to switch between an ON state in which the emitter electrode 9 and the collector electrode 10 are conducting through the layer structure and an OFF state in which the emitter electrode 9 and the collector electrode 10 are not conducting through the layer structure. In addition, the threshold voltage of the gate electrode 7b is higher than the threshold voltage of the gate electrode 7a. Here, α state in which the temperature of the layer structure is lower than the threshold temperature is defined as an α state. In addition, a condition that the switching current, which is a current value at the time of the switching operation for switching to the ON state or the OFF state, is less than the threshold current is defined as a β condition. In addition, α state in which the temperature of the layer structure is equal to or higher than the threshold temperature is defined as a γ state. In addition, a condition that the switching current is equal to or larger than the threshold current is defined as a δ condition. In the α state and the β condition, the switching operation is performed using the gate electrode 7a. In addition, in the γ state or the 5 condition, the switching operation is performed using the gate electrode 7b. Then, in the method for driving the semiconductor device, before the switching operation for switching to the OFF state is performed, the voltage applied to the gate electrode not used for the switching operation is switched.

[0196] According to this configuration, even when the threshold voltage of the gate electrode fluctuates with the change in the operating temperature, occurrence of malfunction of the semiconductor device can be effectively suppressed by selectively using a plurality of gate electrodes having different threshold voltages according to the operating temperature. In addition, since an increase in dI.sub.on/dt or dV.sub.off/dt can be suppressed, the turn-off loss can be reduced.

[0197] It should be noted that when there is no particular limitation, the order in which each piece of treatment is performed can be changed.

[0198] In addition, even when another configuration exemplified in the specification of the present application is appropriately added to the above configuration, that is, even when another configuration in the specification of the present application not referred to as the above configuration is appropriately added, a similar effect can be produced.

[0199] In addition, according to the preferred embodiments described above, in the method for driving a semiconductor device, the semiconductor device includes a p.sup.+-type collector region 2 partially provided in a surface layer on the second surface, an n.sup.+-type collector layer 19 partially provided in a surface layer in the p.sup.+-type collector region 2, a gate insulating film 16 provided in contact with the p.sup.+-type collector region 2 sandwiched between the n-type base layer 1 and the n.sup.+-type collector layer 19, and a gate electrode 17 being a gate electrode formed in contact with the gate insulating film 16. According to this configuration, by combining not only the plurality of gates on the first main surface but also the gates on the second main surface, the carrier density accumulated inside the IGBT can be controlled also from the second main surface (collector surface) side. As a result, the control time of the carrier density can be shortened, and the accuracy of the control can be improved, which is effective to reduce the loss or improve the accuracy of the waveform control.

Modifications of Preferred Embodiments Described Above

[0200] In the preferred embodiments described above, a semiconductor device having an enhancement n-channel MOSFET structure has been described, but a semiconductor device having a depression channel MOSFET structure can also be applied.

[0201] In addition, although the IGBT is shown as an example of the multi-gate semiconductor device, a MOSFET is also applicable.

[0202] In addition, the minimum necessary number of gates of the multi-gate semiconductor device is two, and two or more gates can be applied.

[0203] In addition, in the preferred embodiments described above, what is called a vertical MOSFET has been described, but a case of being applied to a horizontal MOSFET can also be assumed.

[0204] In addition, in the preferred embodiments described above, a trench semiconductor device has been described, but it is also assumed that the present invention is applied to a planar semiconductor device having no trench.

[0205] In the preferred embodiments described above, quality of material, material, dimensions, shape, relative arrangement relationship, or condition of implementation of each component may be described, but these are one example in all aspects, and the present invention is assumed not to be limited to those described in the preferred embodiments.

[0206] Therefore, innumerable modifications not exemplified and their equivalents are assumed within the scope of the techniques disclosed in the specification of the present application. For example, a case of deforming, adding, or omitting at least one component, and furthermore, a case of extracting at least one component in at least one preferred embodiment to combine the extracted component with a component in another preferred embodiment are assumed to be included.

[0207] In addition, in the preferred embodiments described above, when a material name or the like is described without being particularly designated, as long as no contradiction arises, the material is assumed to include a material that contains other additives, such as an alloy.

[0208] In addition, as long as no contradiction arises, when it is described in the above-described preferred embodiments that “one” component is provided, “one or more” components may be provided.

[0209] Furthermore, each component in the preferred embodiments described above is a conceptual unit, and the scope of the technology disclosed in the specification of the present application is assumed to include a case where one component includes a plurality of structures, a case where one component corresponds to part of a structure, and furthermore, a case where a plurality of components are included in one structure.

[0210] In addition, each component in the preferred embodiments described above is assumed to include structures having other structures or shapes as long as the same function is exhibited.

[0211] In addition, the description in the specification of the present application is referred to for all purposes related to the present techniques, and none are assumed to be conventional techniques.

[0212] In addition, in the preferred embodiments described above, it has been described that the first conductivity type is n-type and the second conductivity type is p-type, but conversely, the first conductivity type may be p-type and the second conductivity type may be n-type.

[0213] While the disclosure has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore understood that numerous modifications and variations can be devised.