A first phase adjuster adjusts the phase of any one of first and second AC voltages generated in a negative resistance circuit so that a shift amount Φ in a first variable phase shifter falls within a range of 0 degrees≤Φ<180 degrees, and outputs the phase-adjusted AC voltage to the first variable phase shifter, and a second phase adjuster adjusts the phase of the other one of the first and second AC voltages generated in the negative resistance circuit so that a shift amount Φ in a second variable phase shifter falls within a range of 0 degrees≤Φ<180 degrees, and outputs the phase-adjusted AC voltage to the second variable phase shifter.

A method is provided for enhancing the detection of the start time of a reference oscillator (4) of a super-regenerative receiver (1), which includes the reference oscillator, a bias current generator (7), an oscillation detector (6), and an impedance matching unit (3). Following the supply of the bias current (i_vco) after receiving the activation control signal (Sosc), an oscillation detection is performed by the oscillation detector (6), and once oscillation is detected, an additional amplification current (iboost) dependent on the envelope of the detected oscillation, of an amplification current generation circuit is supplied to the reference oscillator (4) in addition to the bias current to amplify the oscillation signal to be above a critical oscillation start threshold so as to precisely define the start time of the oscillator, and enable the oscillation detector (6) to order the stoppage of oscillation of the reference oscillator (4).

An inductive switch comprises an inductor that has a primary metallic winding having a boundary configured in shape of a figure eight, such as in two loops, and a plurality of secondary metallic windings arranged within the boundary of the primary metallic winding. The inductive switch includes a plurality of switches, each switch arranged in series with a respective one of the plurality of secondary metallic windings. An equal number of the secondary windings is arranged within each loop. A tunable inductor comprises at least one main metallic loop and at least one secondary metallic loop, wherein the at least one secondary metallic loop comprises a switch that is arranged to configure the at least one secondary metallic loop into at least one shorted metallic loop or at least one closed metallic loop. The at least one shorted loop is floating.

Networks of superharmonic injection-locked (SHIL) electronic oscillators can be used to emulate Ising machines for solving difficult computational problems. The oscillators can be simulated or implemented in hardware (e.g., with LC oscillators) and are coupled to each other with links whose connection strengths are weighted according to the problem being solved. The oscillators' phases may be measured with respect to reference signal(s) from one or more reference oscillators, each of which emits a reference signal but does not receive input from any other oscillator. Sparsely connected networks of SHIL oscillators and reference oscillators can be used as Viterbi decoders that do not suffer from the information bottleneck between logic computational blocks and memory in digital computing systems. Sparsely connected networks of SHIL oscillators and reference oscillators can also be programmed to act as Boolean logic gates that operate in both forward and backward directions, enabling multipliers that can factor numbers.

Apparatus and methods for generating multiple oscillating signals. An example circuit generally includes a first voltage-controlled oscillator (VCO) circuit and a second VCO circuit having a differential bias input coupled to a differential output of the first VCO circuit. At least one of the first VCO circuit or the second VCO circuit generally includes: a pair of cross-coupled transistors comprising a first transistor and a second transistor, a first inductive element coupled between a first node and the drain of the first transistor, a second inductive element coupled between the first node and the drain of the second transistor, a third transistor having a drain coupled to the drain of the first transistor and having a source coupled to a second node, and a fourth transistor having a drain coupled to the drain of the second transistor and having a source coupled to the second node.

A real-time clock module includes an oscillation circuit, a storage unit that stores adjustment data used to adjust an oscillation frequency of the oscillation circuit, a data abnormality determination circuit that compares first data based on the adjustment data with second data based on the adjustment data to determine whether or not at least one of the first data and the second data is abnormal, and a flag register that holds a data abnormality flag in which a first value indicating that the first data and the second data are normal, or a second value indicating that at least one of the first data and the second data is abnormal is set, based on a signal from the data abnormality determination circuit.

An apparatus and system for a clock buffer. The clock buffer comprises a source follower, and the source follower comprises a voltage source and a resistor.

An apparatus and system for a clock buffer. The clock buffer comprises a source follower, and the source follower comprises a voltage source and a resistor.

A system includes a sensor integrated circuit (IC), including a driver adapted to be coupled to an oscillator, the driver including first and second transistors. The sensor IC includes an amplitude control amplifier coupled to the first transistor. The sensor IC also includes a common mode control amplifier coupled to the second transistor. The sensor IC includes a handover control circuit coupled to the amplitude control amplifier and configured to hand off an operation from the sensor IC to a different sensor IC, the handover control circuit including a resistor network coupled to a switch network.

A package on a die having a low resistive substrate, wherein the package comprises an inductor on low-k dielectric and a capacitor on high-k dielectric. The stacked arrangement having different dielectric materials may provide an inductor having a high Q-factor while still having a high capacitance density. In addition, moving the inductor from the die to the package and fabricating the high density capacitor on the package reduces the silicon area required permitting smaller RF/analog blocks on the chip.