A system of free running oscillators synchronized to the lowest frequency running one and following PVT variation generates a system clock. A method is particularly applicable to clock relatively small clock domains within a multi-core chip containing thousands of cores, and where the clock domain encompasses one or more cores and additional logic blocks. The resulting system clock is divided by 2.sup.k using latches or flip-flops to achieve a symmetric 50-50 duty cycle of the system clock. Further, such PVT insensitive system clock can be used as a reference for a PLL or DLL generated clock for the domain.

A system of free running oscillators synchronized to the lowest frequency running one and following PVT variation generates a system clock. A method is particularly applicable to clock relatively small clock domains within a multi-core chip containing thousands of cores, and where the clock domain encompasses one or more cores and additional logic blocks. The resulting system clock is divided by 2.sup.k using latches or flip-flops to achieve a symmetric 50-50 duty cycle of the system clock. Further, such PVT insensitive system clock can be used as a reference for a PLL or DLL generated clock for the domain.

An on-chip capacitance measurement method and associated systems and devices are provided. Embodiments described herein rely on using the capacitor under test in an on-chip relaxation oscillator configuration whose charging/discharging currents, supply voltage, and output frequency are measured individually in a measurement block. The voltage thresholds of the relaxation oscillation are calculated from the circuit elements and the measured supply voltage. Because the oscillation frequency of the relaxation oscillator is a function of the capacitance under test, the charging/discharging currents, and the supply voltage (via voltage thresholds), the capacitance under test can be calculated using the measured values of the other quantities. Embodiments described herein provide an accurate, low-power, small-area on-chip system capable of measuring capacitance with high accuracy. An algorithm employing the above method and apparatus for tuning a crystal oscillator is also provided. Relevant circuit implementations used in the on-chip measurement system are also disclosed.

An on-chip capacitance measurement method and associated systems and devices are provided. Embodiments described herein rely on using the capacitor under test in an on-chip relaxation oscillator configuration whose charging/discharging currents, supply voltage, and output frequency are measured individually in a measurement block. The voltage thresholds of the relaxation oscillation are calculated from the circuit elements and the measured supply voltage. Because the oscillation frequency of the relaxation oscillator is a function of the capacitance under test, the charging/discharging currents, and the supply voltage (via voltage thresholds), the capacitance under test can be calculated using the measured values of the other quantities. Embodiments described herein provide an accurate, low-power, small-area on-chip system capable of measuring capacitance with high accuracy. An algorithm employing the above method and apparatus for tuning a crystal oscillator is also provided. Relevant circuit implementations used in the on-chip measurement system are also disclosed.

An oscillator circuit includes an initial level setting circuit configured to operate in an on-state during an initial operation of the oscillator circuit to supply a first level voltage to a first node and a second level voltage to a second node, a switching circuit configured to connect a power supply voltage terminal and a ground terminal to the first or second node in response to first and second clock signals having different phases after the initial operation, a signal generation circuit connected between the first and second nodes and configured to perform charging and discharging operations based on a potential difference between the first and second nodes, and generate first and second voltages determined by the charging and discharging operations, and an inverter circuit configured to generate the first clock signal based on the first voltage, and generate the second clock signal based on the second voltage.

An oscillator circuit includes an initial level setting circuit configured to operate in an on-state during an initial operation of the oscillator circuit to supply a first level voltage to a first node and a second level voltage to a second node, a switching circuit configured to connect a power supply voltage terminal and a ground terminal to the first or second node in response to first and second clock signals having different phases after the initial operation, a signal generation circuit connected between the first and second nodes and configured to perform charging and discharging operations based on a potential difference between the first and second nodes, and generate first and second voltages determined by the charging and discharging operations, and an inverter circuit configured to generate the first clock signal based on the first voltage, and generate the second clock signal based on the second voltage.

An oscillating signal generator circuit includes an oscillator circuit, a feedback circuit, and a voltage regulator circuit. The oscillator circuit is configured to generate a first and second oscillating signal at a first and second output terminal according to a first reference voltage. The first and second oscillating signals are a differential pair of signals. The oscillator circuit includes a common mode sensing circuit coupled between the first and second output terminals. The common mode sensing circuit is configured to sense a common mode component of the first and second oscillating signals so as to generate a sense voltage. The feedback circuit, coupled to the common mode sensing circuit, is configured to generate a feedback voltage according to the sense voltage. The voltage regulator circuit is coupled to the oscillator circuit and the feedback circuit, and configured to regulate a supply voltage so as to generate the first reference voltage.

An oscillating signal generator circuit includes an oscillator circuit, a feedback circuit, and a voltage regulator circuit. The oscillator circuit is configured to generate a first and second oscillating signal at a first and second output terminal according to a first reference voltage. The first and second oscillating signals are a differential pair of signals. The oscillator circuit includes a common mode sensing circuit coupled between the first and second output terminals. The common mode sensing circuit is configured to sense a common mode component of the first and second oscillating signals so as to generate a sense voltage. The feedback circuit, coupled to the common mode sensing circuit, is configured to generate a feedback voltage according to the sense voltage. The voltage regulator circuit is coupled to the oscillator circuit and the feedback circuit, and configured to regulate a supply voltage so as to generate the first reference voltage.

The present disclosure provides an oscillating circuit and an electronic device; the oscillating circuit includes a capacitor charging and discharging circuit unit, a voltage comparison circuit unit and a threshold voltage generation circuit unit; the oscillating circuit uses the capacitor charging and discharging and the hysteresis effect of the capacitor charging and discharging circuit unit to achieve oscillation based on the negative feedback regulation constituted by the voltage comparison circuit unit and the threshold voltage generation circuit unit, which is different from the traditional oscillating circuit based on capacitance and inductance; the oscillating circuit does not adopts inductors, has relatively low power consumption, and outputs oscillation signals with frequencies that vary with currents, and when the oscillating circuit is used to provide clock signals for the sensor, it can be integrated with a sensor signal processing circuit to realize the miniaturization and integration of the sensor system.

The present disclosure provides an oscillating circuit and an electronic device; the oscillating circuit includes a capacitor charging and discharging circuit unit, a voltage comparison circuit unit and a threshold voltage generation circuit unit; the oscillating circuit uses the capacitor charging and discharging and the hysteresis effect of the capacitor charging and discharging circuit unit to achieve oscillation based on the negative feedback regulation constituted by the voltage comparison circuit unit and the threshold voltage generation circuit unit, which is different from the traditional oscillating circuit based on capacitance and inductance; the oscillating circuit does not adopts inductors, has relatively low power consumption, and outputs oscillation signals with frequencies that vary with currents, and when the oscillating circuit is used to provide clock signals for the sensor, it can be integrated with a sensor signal processing circuit to realize the miniaturization and integration of the sensor system.