A real-time clock module includes an oscillation circuit, a storage unit that stores adjustment data used to adjust an oscillation frequency of the oscillation circuit, a data abnormality determination circuit that compares first data based on the adjustment data with second data based on the adjustment data to determine whether or not at least one of the first data and the second data is abnormal, and a flag register that holds a data abnormality flag in which a first value indicating that the first data and the second data are normal, or a second value indicating that at least one of the first data and the second data is abnormal is set, based on a signal from the data abnormality determination circuit.

An oscillator wafer-level-package structure is provided, comprising a bottom layer, an oscillator crystal and a capping layer. The bottom layer includes an upper plane, the capping layer includes a lower plane, and the oscillator crystal is disposed between the bottom layer and the capping layer and includes at least one cavity. An upper seal ring and a lower seal ring are respectively surrounding the oscillator crystal such that the oscillator crystal is sealed in between the capping layer and the bottom layer by employing the upper and lower seal rings. In addition, a diffusion barrier is further disposed in the upper seal ring and in the lower seal ring for avoiding interface diffusion. Moreover, the present invention adopts the same material for fabricating the capping layer, the oscillator crystal and the bottom layer to achieve an optimal thermal stress result when realizing the packaging structure.

An oscillator wafer-level-package structure is provided, comprising a bottom layer, an oscillator crystal and a capping layer. The bottom layer includes an upper plane, the capping layer includes a lower plane, and the oscillator crystal is disposed between the bottom layer and the capping layer and includes at least one cavity. An upper seal ring and a lower seal ring are respectively surrounding the oscillator crystal such that the oscillator crystal is sealed in between the capping layer and the bottom layer by employing the upper and lower seal rings. In addition, a diffusion barrier is further disposed in the upper seal ring and in the lower seal ring for avoiding interface diffusion. Moreover, the present invention adopts the same material for fabricating the capping layer, the oscillator crystal and the bottom layer to achieve an optimal thermal stress result when realizing the packaging structure.

A thin-film heater according to one or more embodiments may include an insulated substrate and metal wiring patterned thereon to extend between both terminals of the metal wiring. The metal wiring has a resistance of 10Ω or less between the terminals. The metal wiring includes a heat-generating layer made of a material that recrystallizes at a temperature of 200° C. or lower.

A thin-film heater according to one or more embodiments may include an insulated substrate and metal wiring patterned thereon to extend between both terminals of the metal wiring. The metal wiring has a resistance of 10Ω or less between the terminals. The metal wiring includes a heat-generating layer made of a material that recrystallizes at a temperature of 200° C. or lower.

A quartz crystal device includes a package, a pedestal, and a crystal element. The pedestal is disposed in the package. The crystal element is bonded to the pedestal at four points. An angle formed by a center line connecting midpoints of both short sides of the crystal element and a straight line connecting a center point of the center line and each of bonding points is 22° or more and 30° or less.

A quartz crystal device includes a package, a pedestal, and a crystal element. The pedestal is disposed in the package. The crystal element is bonded to the pedestal at four points. An angle formed by a center line connecting midpoints of both short sides of the crystal element and a straight line connecting a center point of the center line and each of bonding points is 22° or more and 30° or less.

The circuit device includes a first MOS transistor of a first conductivity type a source of which is coupled to a first power supply voltage node, a second MOS transistor of a second conductivity type a source of which is coupled to a second power supply voltage node, a first variable resistance circuit which is coupled between a drain of the first MOS transistor and an output node, and which includes a first switch, and a second switch coupled between the drain of the first MOS transistor and the second power supply voltage node. The control circuit performs control of making the first switch OFF and making the second switch ON when the clock signal fails to be output from the output node, and making the first switch ON and making the second switch OFF when the clock signal is output from the output node.

The circuit device includes a first MOS transistor of a first conductivity type a source of which is coupled to a first power supply voltage node, a second MOS transistor of a second conductivity type a source of which is coupled to a second power supply voltage node, a first variable resistance circuit which is coupled between a drain of the first MOS transistor and an output node, and which includes a first switch, and a second switch coupled between the drain of the first MOS transistor and the second power supply voltage node. The control circuit performs control of making the first switch OFF and making the second switch ON when the clock signal fails to be output from the output node, and making the first switch ON and making the second switch OFF when the clock signal is output from the output node.

A clock integrated circuit is provided. The clock integrated circuit includes: a first clock generator which includes a crystal oscillator configured to generate a first clock signal; and a second clock generator which includes a resistance-capacitance (RC) oscillator and a first frequency divider, and is configured to: generate a second clock signal using the first frequency divider based on a clock signal output from the RC oscillator; perform a first calibration operation for adjusting a frequency division ratio of the first frequency divider to a first frequency division ratio based on the first clock signal; and perform a second calibration operation for adjusting the first frequency division ratio to a second frequency division ratio based on a sensed temperature.