A device includes a substrate, a first electrode and a second electrode. The first electrode is disposed on the substrate, and configured to receive an input signal. The second electrode is disposed on the substrate, and configured to output an output signal based on the input signal. When the input signal is configured to oscillate within a first range between a first voltage value and a second voltage value with a first frequency, the output signal is an inverted version of the input signal, and has the first frequency. When the input signal is configured to oscillate within a second range including the first voltage value without the second voltage value with the first frequency, the output signal has a second frequency which is approximately twice of the first frequency.

A device includes a substrate, a first electrode and a second electrode. The first electrode is disposed on the substrate, and configured to receive an input signal. The second electrode is disposed on the substrate, and configured to output an output signal based on the input signal. When the input signal is configured to oscillate within a first range between a first voltage value and a second voltage value with a first frequency, the output signal is an inverted version of the input signal, and has the first frequency. When the input signal is configured to oscillate within a second range including the first voltage value without the second voltage value with the first frequency, the output signal has a second frequency which is approximately twice of the first frequency.

A local oscillator (LO) circuit includes a voltage controlled oscillator (VCO) configured to receive an output of a phase locked loop (PLL) circuit, the VCO coupled to a clock gating circuit configured to generate a VCO output signal (vco_g), a local oscillator (LO) divider configured to receive the VCO output signal (vco_g) and a local oscillator (LO) preset signal, the LO preset signal configured to set the LO divider to a predetermined initial phase, a programmable divider configured to receive a divider signal and the VCO output signal (vco_g) and generate a local oscillator (LO) phase detection trigger signal, Fv, a toggling accumulator coupled to an output of the programmable divider, the toggling accumulator configured to receive the divider signal and the LO phase detection trigger signal, Fv, and generate a counter signal, and a decision logic configured to receive a sample enable signal and the counter signal and adjust the programmable divider based on the sample enable signal and the counter signal.

A frequency multiplier includes an input section having inputs to receive an input signal having an input frequency, a mixer section, and an output section magnetically coupled to the input section and generating an output signal in response to the input signal. The mixer section may be coupled to the input section by a common mode node forming a path for a common mode current to flow to the mixer section and be magnetically coupled to the common mode node. The input section may generate a signal current, and the mixer section may be magnetically coupled to the input section and be directly capacitively coupled to the input section through a capacitor in a signal current path. The mixer section may have differential inputs capacitively coupled to the input section and also be coupled to the input section through a current path. A current helper section may be coupled to the current path.

A method of frequency doubling includes receiving a first clock that has a fifty percent duty cycle and is a two-phase clock having a first phase and a second phase; outputting a second clock using a multiplexer by selecting one of the first phase and the second phase of the first clock in accordance with a third clock; delaying the second clock into a fourth clock using a recirculating delay circuit; and using a divide-by-two circuit to output the third clock in accordance with the fourth clock.

A method of frequency doubling includes receiving a first clock that has a fifty percent duty cycle and is a two-phase clock having a first phase and a second phase; outputting a second clock using a multiplexer by selecting one of the first phase and the second phase of the first clock in accordance with a third clock; delaying the second clock into a fourth clock using a recirculating delay circuit; and using a divide-by-two circuit to output the third clock in accordance with the fourth clock.

Methods, systems, and devices for wireless communication are described. An internal state of a frequency divider of a local oscillator (LO) may be stored using a storage device in order to facilitate phase flipping of one or more signals output by the LO. The frequency divider may also include a pulse swallower that swallows a pulse of a signal input into the frequency divider. Using one or more power supply cutting switches in combination with a storage device and pulse swallower, high speed and reliable phase flipping of LO signals may be performed.

A dual-frequency-output crystal controlled oscillator includes a crystal resonator, an oscillator circuit, a first output terminal, a second output terminal, and a selection circuit. The crystal resonator includes an input terminal for measurement and an output terminal for measurement. The oscillator circuit is configured to amplify an output of the crystal resonator; a first output terminal configured to output a first frequency based on an output from the oscillator circuit. The second output terminal is configured to output a second frequency lower than the first frequency based on the output from the oscillator circuit. The selection circuit is configured to turn on/off an output of the first frequency. The input terminal for measurement is disposed such that a distance between the input terminal for measurement and the second output terminal is longer than a distance between the input terminal for measurement and the first output terminal.

A clock generator has a buffer stage circuit, a passive mixer, and a channel selecting circuit. The buffer stage circuit receives a plurality of first reference clocks having a same first frequency but different phases. The passive mixer receives the first reference clocks from the buffer stage circuit, receives a plurality of second reference clocks having a same second frequency but different phases, and mixes the first reference clocks and the second reference clocks to generate a mixer output, wherein the second frequency is different from the first frequency. The channel selecting circuit extracts a plurality of third reference clocks from the mixer output, wherein the third reference clocks have a same third frequency but different phases, and the third frequency is different from the first frequency and the second frequency.

The waveform generator (10) comprises a switch (13). The waveform generator (10) comprises a transformer (15) having a primary side circuit and a secondary side circuit. The primary side circuit has a first terminal arranged to be conductively coupled to a DC voltage source, and a second terminal conductively coupled to the switch (13). The waveform generator (10) further comprises a controller (11) arranged to supply a drive signal to the switch for switching the switch between on and off states. The controller (11) is arranged to adjust the frequency of the drive signal so as to control at least one of the peak voltage and the duty cycle of a waveform generated by the waveform generator (10). The frequency of the drive signal may be adjusted as the voltage level of the DC voltage source remains constant. The frequency of the drive signal may be adjusted in response to a change in the voltage level of the DC voltage source.