A semiconductor device includes a resistor element connected to one and another end of a crystal oscillator, and an adjustable current type inverter element having an input connected to one end of the resistor element and an output connected to another end of the resistor element. A first capacitor element is connected to the input of the inverter element and to ground, and a second capacitor element has one end connected to ground. A first switching element switches a connection state of the one end of the first capacitor element and another end of the second capacitor element. A third capacitor element is connected to the output of the inverter element and to ground, and a fourth capacitor element has one end connected to ground. A second switching element switches a connection state of the one end of the third capacitor element and another end of the fourth capacitor element.

A circuit device includes an oscillation circuit and a processing circuit. The oscillation circuit includes a variable capacitance circuit configured by a capacitor array and oscillates at an oscillation frequency corresponding to the capacitance value of the variable capacitance circuit. First temperature data and second temperature data subsequent to the first temperature data are input to the processing circuit as temperature data. In the period between the start of the capacitance control based on the first temperature data and the start of the capacitance control based on the second temperature data, the processing circuit switches the first capacitance control data corresponding to the first temperature data and the second capacitance control data different from the first capacitance control data in a time-division manner to be output to the variable capacitance circuit.

A signal generator comprises (i) a first set of capacitors at least partially switchably connectable for adjusting a frequency of an oscillator as part of a phase-locked loop and (ii) a second set of capacitors comprised in one or more oscillator control subsystems. A method of controlling the signal generator comprises: (i) acquiring a frequency lock in the phase-locked loop, (ii) calculating, in conjunction with the acquiring of the frequency lock, a systematic capacitance error of the first set of capacitors due to process, voltage, and temperature variations based on the frequency of the oscillator and a switching state of the first set of capacitors, and (iii) calibrating the one or more oscillator control subsystems using the systematic capacitance error, thereby compensating for process, voltage, and temperature variations common between the first set of capacitors and the second set of capacitors.

A method and circuit for linearizing a frequency response of an oscillator controlled by a plurality of capacitor banks are disclosed. In the disclosed method, for each capacitor bank of at least two capacitor banks of the oscillator, a respective sensitivity characteristic of the capacitor bank is determined. Further, a set of reference output frequency control words (FCWs) for an associated set of frequencies of the oscillator are determined. When an input FCW is received and an output FCW is responsively provided based on (i) an interpolation between two reference output FCWs of the set of reference output FCWs and (ii) the respective sensitivity characteristics of the at least two capacitor banks of the oscillator. The output FCW is then applied to the at least two capacitor banks of the oscillator.

A frequency variable oscillator generates a clock having a frequency according to a control signal. A reference current source generates a reference current. A path selector distributes the reference current to a first path and a second path in a time-sharing manner in synchronization with the clock. An F/V conversion circuit includes a capacitor connected to the first path, and charges or discharges the capacitor with the reference current and generates a detection voltage. The reference voltage source includes a resistor connected to the second path, and outputs a reference voltage according to a voltage across the resistor. A feedback circuit adjusts a control signal so that the detection voltage approaches the reference voltage.

Certain aspects relate to a semiconductor die. The semiconductor die includes a voltage-controlled oscillator (VCO), wherein the VCO includes a resonant capacitor, and a resonant inductor coupled in parallel with the resonant capacitor. The resonant inductor includes a first elongated portion and a second elongated portion that are parallel with each other. The semiconductor die also includes a voltage supply line configured to route a supply voltage to the VCO, wherein the voltage supply line includes a first portion that runs parallel with the first and second elongated portions of the resonant inductor and is located between the first and second elongated portions of the resonant inductor.

Relax oscillation circuits have at least one comparison circuit that is structured with a flipped gate transistor and a normal MOS transistor wherein the two transistors having different threshold voltages. The relaxation oscillators are configured for charging and discharging capacitances between the threshold voltages of the flipped gate transistor and the normal MOS transistor by toggling the state of a latching circuit to control the charging and discharging of the capacitances.

Increases of circuit scale and power consumption are suppressed while frequency deviation is kept within a predetermined allowable range. A semiconductor device according to an embodiment includes a variable load capacity circuit including a plurality of load capacity elements coupled in parallel to one end of a crystal resonator and a plurality of switches that are respectively serially coupled to the load capacity elements, and a switch control unit that controls ON/OFF of the switches on the basis of information to be an index of frequency deviation due to temperature change of a frequency signal obtained by oscillating the crystal resonator. The switch control unit changes the number of switches that will be turned ON among the plurality of switches so that an absolute value of the frequency deviation becomes small when the information is not included in a predetermined allowable range.

A biasing circuit for biasing a switching transistor, wherein the switching transistor is used for switching a respective capacitor cell into/out of a capacitor array, wherein the capacitor array comprises one or more such capacitor cells, and wherein the capacitor array is coupled in parallel with a primary inductor to form an inductive/capacitive tank. The biasing circuit comprises a secondary inductor which is inductively coupled to the primary inductor, the secondary inductor configured to provide a bias signal for biasing the switching transistor.

A signal generator comprises (i) a first set of capacitors at least partially switchably connectable for adjusting a frequency of an oscillator as part of a phase-locked loop and (ii) a second set of capacitors comprised in one or more oscillator control subsystems. A method of controlling the signal generator comprises: (i) acquiring a frequency lock in the phase-locked loop, (ii) calculating, in conjunction with the acquiring of the frequency lock, a systematic capacitance error of the first set of capacitors due to process, voltage, and temperature variations based on the frequency of the oscillator and a switching state of the first set of capacitors, and (iii) calibrating the one or more oscillator control subsystems using the systematic capacitance error, thereby compensating for process, voltage, and temperature variations common between the first set of capacitors and the second set of capacitors.