Some embodiments include apparatuses and methods of using the apparatuses. One of the apparatuses includes an inductor included in an integrated circuit device, and a first oscillator and a second oscillator included in the integrated circuit device. The first oscillator includes a first terminal coupled to a conductive path of the inductor to provide a first signal. The second oscillator includes a second terminal coupled to the conductive path to provide a second signal. The first and second signals have different frequencies.

A crystal oscillator with a configuration that allows for reduction of power consumption includes a crystal element, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a crystal element. The crystal element includes a first terminal coupled to a control terminal of the seventh transistor and a second terminal coupled to a first terminal of the seventh transistor. The second transistor includes a control terminal coupled to an output terminal of the crystal oscillator and a first terminal of the ninth transistor.

A low power crystal oscillator is provided. The crystal oscillator includes a gain stage circuit having a first gain stage input coupled at a first oscillator terminal and configured to receive a first oscillator signal of a crystal. A first bias circuit is configured to generate a first bias voltage based on the first oscillator signal. A reference circuit is configured to generate a reference current based on the first bias voltage. A comparator circuit is configured to generate a clock signal based on the first oscillator signal and the first bias voltage. The comparator circuit includes a second bias circuit configured to generate a second bias voltage. The gain stage circuit includes a second gain stage input coupled to receive the second bias voltage.

A method and crystal oscillator circuit match a supply voltage with a drive level of a crystal. The crystal oscillator circuit is based on a Pierce oscillator circuit which further includes a capacitor C.sub.d. The capacitor C.sub.d together with the load capacitor act as a capacitive voltage divider and the capacitance of this capacitor may be selected to reduce the supply voltage to match the drive level of the crystal oscillator without affecting the oscillation margin of the crystal.

A clock integrated circuit is provided. The clock integrated circuit includes: a first clock generator which includes a crystal oscillator configured to generate a first clock signal; and a second clock generator which includes a resistance-capacitance (RC) oscillator and a first frequency divider, and is configured to: generate a second clock signal using the first frequency divider based on a clock signal output from the RC oscillator; perform a first calibration operation for adjusting a frequency division ratio of the first frequency divider to a first frequency division ratio based on the first clock signal; and perform a second calibration operation for adjusting the first frequency division ratio to a second frequency division ratio based on a sensed temperature.

An oscillator includes first and second capacitors, an inverter, a voltage shifting circuit, and a hysteresis buffer. The first and second capacitors have first terminals adapted to be coupled to respective first and second nodes, and second terminals coupled to ground. The inverter has an input coupled to the first node, and an output coupled to the second node. The voltage shifting circuit is coupled to the first and second nodes and has an input for receiving a tuning signal. The voltage shifting circuit changes an average voltage at the first node according to the tuning signal when an oscillation occurs in response to a crystal being coupled between the first and second nodes. The hysteresis buffer has an input coupled to one of first node and the second node, and an output for providing a clock signal having a duty cycle responsive to the tuning signal.

Low voltage crystal oscillator having native NMOS transistors used for coupling/decoupling to/from GPIO. The native NMOS transistors function properly at a low supply voltage when on (low resistance) and a high supply voltage when off (high resistance). Oscillator Gm driver bias resistors are repurposed to degenerate the native NMOS transistors when they are off, thereby reducing the leakage current thereof (oscillator circuit decoupled from GPIO nodes). This ensures compliance with the CMOS IIH leakage current specification during an external clock (EC) mode at a high supply voltage.

An oscillator includes a constant current generator configured to generate a constant current by maintaining a predetermined potential difference between both a first end and a second end of a resistor, and an oscillating element configured to output a clock signal corresponding to a charge and discharge cycle of a capacitor based on a bias current corresponding to the constant current.

An oscillator arrangement is provided, comprising a relaxation oscillator having an active state and an inactive state; a bias current circuit portion arranged to provide a bias current to the relaxation oscillator during said active state; and an electronic switch arranged to isolate said relaxation oscillator from the bias current circuit portion when in said inactive state. The oscillator arrangement is arranged to store an internal voltage value associated with said bias current and the bias current circuit portion is arranged to use the stored internal voltage value to generate the bias current when the oscillator is started up from the inactive state to the active state.

To prevent an undesired operating mode of voltage-controlled oscillation (VCO) circuitry from dominating a desired operating mode (e.g., an in-phase operating mode or an out-of-phase operating mode), a supply reset and ramp pulse may be provided to the VCO circuitry when switching to a new mode, such that supply voltage to the VCO circuitry is reset (e.g., set to 0 V or another reference voltage), and gradually increased or ramped up back to a steady-state voltage (e.g., used to maintain a mode) within a time duration. Additionally or alternatively, a switch control bootstrap pulse may be provided to the VCO circuitry that is bootstrapped to (e.g., applied instantaneously or concurrently with) switching the VCO circuitry to the new mode. After a time duration, the VCO circuitry may switch back to a steady-state voltage (e.g., used to maintain the new mode).