A detector includes a frequency multiplier and a transceiving node. The frequency multiplier includes a first terminal, a second terminal and an output terminal. The first terminal is used to receive a first injection signal having a first frequency. The output terminal is used to output an output signal. The second terminal is used to receive a second injection signal having a second frequency. The frequency multiplier is used to output the output signal at a frequency substantially equal to a multiple of the first frequency by injection locking and pull the output signal to the second frequency by injection pulling. The transceiving node is coupled to the output terminal and the second terminal of the frequency multiplier. The transceiving node is used to transmit the output signal, and receive a received signal having a third frequency. The received signal is used to update the second injection signal.

An oscillation module includes: an oscillation circuit; a multiplication circuit which is provided at a stage subsequent to the oscillation circuit and is operated by differential motion; and an output circuit which is provided at a stage subsequent to the multiplication circuit.

A wiring pattern for oscillation input signal and a wiring pattern for oscillation output signal are provided on a printed circuit board, and a wiring pattern for ground power source voltage is arranged in a region therebetween. A quartz crystal unit is connected between the wiring pattern for oscillation input signal and the wiring pattern for oscillation output signal and one ends of capacitors serving as load capacitors thereof are connected to the wiring pattern for ground power source voltage. Further, a wiring pattern for VSS is arranged so as to enclose these wiring patterns, and a wiring pattern for VSS is arranged also in a lower layer in addition thereto. By this means, reduction of a parasitic capacitance between an XIN node and an XOUT node, improvement in noise tolerance of these nodes and others can be achieved.

A circuit device includes an oscillation circuit configured to generate an oscillation signal and a temperature compensation circuit configured to perform temperature compensation for an oscillation frequency of the oscillation signal. The temperature compensation circuit includes a first reference current generation circuit configured to generate a first reference current, a second reference current generation circuit configured to generate a second reference current, a first compensation circuit configured to perform temperature compensation for the oscillation frequency in a first temperature range based on the first reference current, and a second compensation circuit configured to perform temperature compensation for the oscillation frequency in a second temperature range, which is higher than the first temperature range in temperature, based on the second reference current. The first reference current generation circuit reduces the first reference current as a temperature rises, or the second reference current generation circuit reduces the second reference current as the temperature drops.

A detector includes an oscillation source, a frequency multiplier, a transceiver and a demodulator. The oscillation source generates a first injection signal with a first frequency. The frequency multiplier receives the first injection signal, outputs an output signal and receives a second injection signal with a second frequency. The frequency multiplier uses injection locking to lock a frequency of the output signal at a multiple of the first frequency, and uses injection pulling to pull the frequency of the output signal to the second frequency. The transceiver transmits the output signal and receives a received signal with a third frequency for updating the second injection signal. The demodulator performs a demodulation operation according to the output signal so as to generate a displacement signal.

A system for reducing clock jitter may include first jitter reducing circuitry. The first jitter reducing circuitry may be arranged between an input clock signal node carrying an input clock signal and an output clock signal node carrying an output clock signal. The first jitter reducing circuitry may include a first intermediate input clock signal node and a first intermediate output clock signal node. The first jitter reducing circuitry may include a first clock delay circuit, which may be configured to: (1) delay a first intermediate input clock signal received on the first intermediate input clock signal node by an odd integer multiple of one half of a period, and (2) invert the first intermediate input clock signal. The first jitter reducing circuitry may also include a first connection, which may be from the first intermediate output clock signal node to the first intermediate input clock signal node.

This disclosure is directed to a Voltage-Controlled Oscillator (VCO) with improved phase noise compared to other VCOs. The VCO may include a first cell and a second cell separated by common-mode (CM) isolation circuitry to reduce an amplitude of CM noise at an output signal. The CM isolation circuitry may inductively couple the first cell to the second cell for generating the output signal based on a resonant frequency range including resonant frequencies of the CM isolation circuitry, the first cell, and the second cell. As such, the first cell and the second cell may each include a portion of an entirety of the CM noise. In some cases, the portions of the CM noise on the first cell and/or the second cell may improve a signal to noise ratio of the output signal.

This disclosure is directed to a Voltage-Controlled Oscillator (VCO) with improved phase noise compared to other VCOs. The VCO may include a first cell and a second cell separated by common-mode (CM) isolation circuitry to reduce an amplitude of CM noise at an output signal. The CM isolation circuitry may inductively couple the first cell to the second cell for generating the output signal based on a resonant frequency range including resonant frequencies of the CM isolation circuitry, the first cell, and the second cell. As such, the first cell and the second cell may each include a portion of an entirety of the CM noise. In some cases, the portions of the CM noise on the first cell and/or the second cell may improve a signal to noise ratio of the output signal.

This disclosure is directed to a Voltage-Controlled Oscillator (VCO) with improved phase noise compared to other VCOs. The VCO may include a first cell and a second cell separated by common-mode (CM) isolation circuitry to reduce an amplitude of CM noise at an output signal. The CM isolation circuitry may inductively couple the first cell to the second cell for generating the output signal based on a resonant frequency range including resonant frequencies of the CM isolation circuitry, the first cell, and the second cell. As such, the first cell and the second cell may each include a portion of an entirety of the CM noise. In some cases, the portions of the CM noise on the first cell and/or the second cell may improve a signal to noise ratio of the output signal.

A circuit for detecting, controlling, and maintaining optimal output swing for a noise performance at a given power with an improved operating range is provided. The circuit includes a Voltage Controlled Oscillator (VCO) (102), a peak detection circuit (104) and an Analog Bias Controller (108). The VCO includes a bias control that is connected to the output swing of the VCO. The peak detection circuit is added at an output of the VCO. The peak detection circuit detects an output swing of the VCO and controls the output swing by controlling bias of the VCO using a feedback loop. An output voltage of the peak detection circuit is proportional to the output swing of the VCO. The Analog Bias Controller compares the output voltage of the peak detection circuit to a reference (VDD) to maintain the output swing of the VCO at a constant level that corresponds to an internally generated reference.