Systems and methods are provided for aligning amplitude and phase signals in a polar receiver. A receiver generates digital amplitude and phase signals representing the amplitude and phase of a modulated input signal. At least one of the digital signals is filtered using a fractional delay filter with a variable delay. The delay of the fractional delay filter is adjusted to align the amplitude and phase signals. In some embodiments, an error vector magnitude is determined by comparing in-phase and quadrature values of the signal with values corresponding to a constellation point, and the delay is adjusted based on the error vector magnitude. The fractional delay filter may be a finite impulse response filter with coefficients stored in a lookup table that correspond to different delays.

In one embodiment a transmitter is disclosed. The transmitter comprises an envelope tracking amplifier circuit comprising a power amplifier; a radiofrequency path configured to couple a radiofrequency component of an input signal to an input of the power amplifier; an envelope path configured to modulate a supply voltage of the power amplifier with an envelope signal, the envelope path comprising an envelope shaping module configured to shape an envelope of the input signal using an envelope shaping function to obtain the envelope signal; and a delay block configured to vary the relative timing alignment of the radiofrequency path and the envelope path; storage for an indication of the envelope shaping function to be used by the envelope shaping module; and a processor operable to, iteratively search for a value of a first parameter of a generic envelope shaping function, by applying a test signal to the envelope tracking amplifier circuit and controlling the delay block over a sweep of the relative timing alignments between the radiofrequency path and the envelope path; determining an average measure of distortion of output of the envelope tracking amplifier circuit for the sweep of relative timing alignments; comparing the average measure of distortion of output of the envelope tracking amplifier circuit with an average measure of distortion of the output of the envelope tracking amplifier circuit for a previous iteration; and selecting for the envelope shaping function the value of the first parameter from the previous iteration if the average measure of distortion of the output of the envelope tracking amplifier circuit for the previous iteration is lower than the average measure of distortion of the output of the envelope tracking amplifier circuit determined; and storing an indication of the envelope shaping function with the selected value for the first parameter in the storage.

Systems and methods for adjusting a phase step size of a clock data recover (CDR) circuit are described according to aspects of the present disclosure. In certain aspects, a method for adjusting a phase step size of a CDR circuit includes sensing a frequency offset of the CDR circuit, and adjusting the phase step size of the CDR circuit based on the sensed frequency offset. The frequency offset may be sensed by sensing a signal level on an integration path of a loop filter of the CDR circuit. The phase step size of the CDR circuit may be adjusted by switching the CDR circuit between a first phase step size and a second phase step size using a modulator (e.g., a sigma-delta modulator).

A shift control circuit includes a first limiter circuit, a phase shifter, a first suppressor, and a reducer. The first limiter circuit limits the amplitude of a control target signal input from a microphone, having undergone A-D conversion by an A-D convener, and frequency differentiation by a pre-emphasis circuit, and having the relative intensity of harmonic components increased. The phase shifter performs, for the control target signal having undergone the amplitude limitation, phase shift on the frequency component within a first frequency range. The first suppressor suppresses, for the control target signal having undergone the phase shift, the frequency component equal to or greater than a second threshold. The reducer suppresses, for the control target signal having the suppressed frequency component, the frequency component within a second frequency range, and outputs as an information signal. A modulator performs frequency modulation on a carrier wave in accordance with the information signal, and a transmitter produces a transmission signal from the carrier wave haying undergone the frequency modulation, and transmits the transmission signal via an antenna.

A shift control circuit includes a first limiter circuit, a phase shifter, a first suppressor, and a reducer. The first limiter circuit limits the amplitude of a control target signal input from a microphone, having undergone A-D conversion by an A-D convener, and frequency differentiation by a pre-emphasis circuit, and having the relative intensity of harmonic components increased. The phase shifter performs, for the control target signal having undergone the amplitude limitation, phase shift on the frequency component within a first frequency range. The first suppressor suppresses, for the control target signal having undergone the phase shift, the frequency component equal to or greater than a second threshold. The reducer suppresses, for the control target signal having the suppressed frequency component, the frequency component within a second frequency range, and outputs as an information signal. A modulator performs frequency modulation on a carrier wave in accordance with the information signal, and a transmitter produces a transmission signal from the carrier wave haying undergone the frequency modulation, and transmits the transmission signal via an antenna.

A signal input from a microphone is A-D converted by an A-D converter, is frequency differentiated by a pre-emphasis circuit, and is input to a shift control circuit. The shift control circuit includes a limiter circuit, a phase shifter, and a harmonic suppressor. The limiter circuit performs amplitude limitation so as to limit the amplitude of the input control target signal to be equal to or less than a first threshold. The phase shifter shifts, for the control target signal having the amplitude limited, a phase of a frequency component within the predetermined frequency range. The harmonic suppressor suppresses, for the control target signal phase-shifted by the phase shifter, a frequency component equal to or greater than a second threshold, and outputs an information signal that is the control target signal having the frequency component of equal to or greater than the second threshold suppressed. The modulator performs frequency modulation on a carrier wave in accordance with the information signal. The transmitter produces a transmission signal from the frequency-modulated carrier wave, and transmits the transmission signal via an antenna.

A signal input from a microphone is A-D converted by an A-D converter, is frequency differentiated by a pre-emphasis circuit, and is input to a shift control circuit. The shift control circuit includes a limiter circuit, a phase shifter, and a harmonic suppressor. The limiter circuit performs amplitude limitation so as to limit the amplitude of the input control target signal to be equal to or less than a first threshold. The phase shifter shifts, for the control target signal having the amplitude limited, a phase of a frequency component within the predetermined frequency range. The harmonic suppressor suppresses, for the control target signal phase-shifted by the phase shifter, a frequency component equal to or greater than a second threshold, and outputs an information signal that is the control target signal having the frequency component of equal to or greater than the second threshold suppressed. The modulator performs frequency modulation on a carrier wave in accordance with the information signal. The transmitter produces a transmission signal from the frequency-modulated carrier wave, and transmits the transmission signal via an antenna.

The invention relates to frequency synthesizer circuits, and in particular to frequency synthesizer circuits characterized by a small channel spacing. Embodiments disclosed include a frequency synthesizer circuit for a radio receiver, the circuit comprising: a digitally controlled oscillator configured to generate an output signal with an output frequency on application of an oscillator enable signal; a delay module; configured to delay an input reference signal to generate a delayed reference signal; and a duty cycle module configured to modulate the oscillator enable signal based on a period of an input reference signal and the delay of the delayed reference signal, such that a ratio between the output frequency and the frequency of the input reference signal is a non-integer.

According to an embodiment, a circuit for quadrate error correction is proposed. The circuit includes a set of first resistors receiving a demodulated low-voltage differential signal from gyroscope sense electrodes; an ICMFB circuit with adjustable current sinks maintaining a low-voltage input level by controlling current; an HV driver circuit creating a high-voltage differential output from the low-voltage input, supplied to gyroscope correction electrodes; a set of second resistors where the input-to-output differential gain is defined by their relative resistances; and an output common-mode feedback circuit adapting the high-voltage output to a low-voltage for the HV driver.