A power amplifier arrangement comprises a power amplifier comprising at least one transistor having a first gate and a second gate. The first gate is configured to receive a radio frequency input signal superimposed with a first control signal, and the second gate is configured to receive a second control signal. The first control signal is a linearization signal varying in relation to an envelope of the input signal and the second control signal is a temperature compensation signal varying in relation to a temperature of the power amplifier, or vice versa.

An amplifier comprises a common emitter stage coupled to a first and a second input, a common base stage coupled to the common emitter stage and to a first and a second output, and a cancellation path coupled to the common emitter stage and the common base stage and to the first and second outputs. The cancellation path generates a first cancellation signal that is 180 degrees out of phase with a first leakage signal at the first output and a second cancellation signal that is 180 degrees out of phase with a second leakage signal at the second output. The cancellation path comprises a first cancellation transistor coupled to the common emitter stage and the common base stage and to the first output and a second cancellation transistor coupled to the common emitter stage and the common base stage and to the second output.

A differential amplifier which does not have an effect of noise resistance deterioration, waveform distortion, and a lower bandwidth while having a wide input range is realized. The differential amplifier does not cause deterioration in a signal quality due to an increase in an input load, and it is not necessary to additionally provide a configuration for generating a reference voltage. The differential amplifier includes a differential amplification circuit and an output circuit for amplifying and outputting a differential output from the differential amplification circuit. The differential amplification circuit includes a first conductive type first differential pair which supplies output currents according to a positive phase input signal and a reverse phase input signal to the output circuit, a second conductive type second differential pair which supplies output currents according to a positive phase input signal and a reverse phase input signal to the output circuit, a detector which detects an operation state of a differential pair, and an alternative current supplying circuit which supplies an alternative current for the output current of the differential pair which has been turned off to the output circuit.

A Class-D amplifier includes a plurality of power rails, a quantizer, and a driver stage. The quantizer and the driver stage have a combined gain. For each power rail of the plurality of power rails, the Class-D amplifier senses a voltage value for the power rail and determines a ramp amplitude based on the sensed voltage value. The Class-D amplifier concurrently switches from the driver stage using a first power rail to a second power rail of the plurality of power rails and switches from the quantizer using the ramp amplitude associated with the first power rail to using the ramp amplitude associated with the second power rail so that the combined gain is constant.

Distributed amplifiers with controllable linearization are provided herein. In certain embodiments, a distributed amplifier includes a differential input transmission line, a differential output transmission line, and a plurality of differential distributed amplifier stages connected between the differential input transmission line and the differential output transmission line at different points or nodes. The distributed amplifier further includes a differential non-linearity cancellation stage connected between the differential input transmission line and the differential output transmission line and providing signal inversion relative to the differential distributed amplifier stages. The differential non-linearity cancellation stage operates with a separately controllable bias from the differential distributed amplifier stages, thereby providing a mechanism to control the linearity of the distributed amplifier.

An on-chip transformer circuit is disclosed. The on-chip transformer circuit comprises a primary winding circuit comprising at least one turn of a primary conductive winding arranged as a first N-sided polygon in a first dielectric layer of a substrate; and a secondary winding circuit comprising at least one turn of a secondary conductive winding arranged as a second N-sided polygon in a second, different, dielectric layer of the substrate. In some embodiments, the primary winding circuit and the secondary winding circuit are arranged to overlap one another at predetermined locations along the primary conductive winding and the secondary conductive winding, wherein the predetermined locations comprise a number of locations less than all locations along the primary conductive winding and the secondary conductive winding.

A variable gain amplifier and an electronic apparatus. The variable gain amplifier includes a first transconductance stage circuit and a second transconductance stage circuit, where the first transconductance stage circuit includes a first amplifying circuit and a second amplifying circuit, the second transconductance stage circuit includes a third amplifying circuit and a fourth amplifying circuit, the first amplifying circuit and the fourth amplifying circuit form a differential input pair, and the second amplifying circuit and the third amplifying circuit form a differential input pair, and where each amplifying circuit of the first amplifying circuit, the second amplifying circuit, the third amplifying circuit, and the fourth amplifying circuit includes a plurality of parallel transistors, and bias control of the plurality of transistors is independent of each other.

The disclosed embodiments relate to the design of an equalizer that uses both cross-coupled cascodes and inductive peaking to reduce distortion in a signal received from a communication channel by attenuating lower frequencies and amplifying higher frequencies. At lower frequencies, when the effects of inductive impedance within the equalizer are negligible, the equalizer essentially functions as a traditional cascode amplifier that presents high gain. At higher frequencies, the increases in inductive impedances within the equalizer act to boost a gain of the equalizer.

An amplifier including a first cascode circuit including a first transistor and a second transistor whose source or emitter is coupled to a drain or a collector of the first transistor, a second cascode circuit being a differential pair with the first cascode circuit, the second cascode circuit including a third transistor whose source or emitter is coupled to a source or an emitter of the first transistor and a fourth transistor whose source or emitter is coupled to a drain or collector of the third transistor, a first feedback path that couples between an output terminal of the third transistor and an input terminal of the first transistor, the first feedback path including a first capacitative element, and a second feedback path that couples between an output terminal of the first transistor and an input terminal of the third transistor, the second feedback path including a second capacitative element.

A receiver circuit may be provided. The receiver circuit may include a first duty cycle adjuster configured to correct a duty cycle of a first output signal pair. The receiver circuit may include a second duty cycle adjuster configured to correct a duty cycle of a second output signal pair, based on the first output signal pair, after the first duty cycle adjuster performs a correction on the duty cycle of the first output signal pair.