A circuit for processing an N-level pulse amplitude modulation (PAM-N) signal according to an embodiment of the present invention comprises: an input unit receiving an input signal; a main amplifier connected to the input unit to amplify the input signal with a first gain; and an output unit outputting an output signal of the main amplifier, and the circuit further comprises an auxiliary amplifier connected in parallel with the main amplifier between the input unit and the output unit to variably amplify at least a portion of the input signal and apply the signal to the output unit according to a linearity improvement control signal corresponding to the output signal.

A dynamic amplifier includes a common-source amplifier configured to receive a gate voltage at a gate node and output a drain current to a drain node; a current mirror configured to mirror the drain current into an output current to an output current; a source capacitor connected to the source node; a load capacitor connected to the output node; a first switch configured to conditionally connect the gate node to an input voltage; a second switch configured to conditionally connect the gate node to a gate-resetting voltage; a third switch configured to conditionally connect the source node to a source-resetting voltage; a fourth switch configured to conditionally connect the drain node to a drain-resetting voltage; and a fifth switch configured to conditionally connect the output node to an output-resetting voltage.

A dynamic amplifier includes a common-source amplifier configured to receive a gate voltage at a gate node and output a drain current to a drain node; a current mirror configured to mirror the drain current into an output current to an output current; a source capacitor connected to the source node; a load capacitor connected to the output node; a first switch configured to conditionally connect the gate node to an input voltage; a second switch configured to conditionally connect the gate node to a gate-resetting voltage; a third switch configured to conditionally connect the source node to a source-resetting voltage; a fourth switch configured to conditionally connect the drain node to a drain-resetting voltage; and a fifth switch configured to conditionally connect the output node to an output-resetting voltage.

The present invention provides an amplifier including an input stage, an amplifier stage, a power stage and a de-gain stage. The input stage is configured to receive an input signal to generate an amplified signal. The amplifier stage is configured to generate a first driving signal and a second driving signal according to the amplified signal. The power stage comprises a first input terminal and a second input terminal, wherein the power stage is coupled to a supply voltage and a ground voltage, for receiving the first driving signal and the second driving signal from the first input terminal and the second input terminal, respectively, and generating an output signal.

The present invention provides an amplifier including an input stage, an amplifier stage, a power stage and a de-gain stage. The input stage is configured to receive an input signal to generate an amplified signal. The amplifier stage is configured to generate a first driving signal and a second driving signal according to the amplified signal. The power stage comprises a first input terminal and a second input terminal, wherein the power stage is coupled to a supply voltage and a ground voltage, for receiving the first driving signal and the second driving signal from the first input terminal and the second input terminal, respectively, and generating an output signal.

A transistor comprises a drain, a gate, a source, a body terminal and a body resistance. The drain is connected to a supply voltage line to receive a supply voltage. The gate is connected to a control voltage line to receive a control voltage. The source is connected to a input line to receive a input radio frequency signal. The body terminal is connected to the drain. The body resistance is disposed between the drain and the body terminal. By the foregoing configuration, the leakage current of the substrate is reduced and the threshold voltage of the transistor is reduced to conform to the present low power design.

A transistor comprises a drain, a gate, a source, a body terminal and a body resistance. The drain is connected to a supply voltage line to receive a supply voltage. The gate is connected to a control voltage line to receive a control voltage. The source is connected to a input line to receive a input radio frequency signal. The body terminal is connected to the drain. The body resistance is disposed between the drain and the body terminal. By the foregoing configuration, the leakage current of the substrate is reduced and the threshold voltage of the transistor is reduced to conform to the present low power design.

A receiver front end (300) having low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch (235) is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. A drain switch (260) is provided between the drain terminals of input FETs to place the input FETs in parallel. This increases the g.sub.m of the input stage of the amplifier, thus improving the noise figure of the amplifier.

A receiver front end (300) having low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch (235) is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. A drain switch (260) is provided between the drain terminals of input FETs to place the input FETs in parallel. This increases the g.sub.m of the input stage of the amplifier, thus improving the noise figure of the amplifier.

A multi-stage amplifier includes a first stage comprising a first common-source amplifier, a first inductive load network comprising a serial connection of a first load resistor and a first load inductor, and a first source network configured to receive a first signal and output a first load signal, and a first inter-stage inductor configured to couple the first load signal to a second signal; and a second stage comprising a second common-source amplifier, a second inductive load network comprising a serial connection of a second load resistor and a second load inductor, and a second source network configured to receive the second signal and output a second load signal, and a second inter-stage inductor configured to couple the second load signal to a third signal, wherein the first load inductor and the second load inductor are laid out to enhance an inter-stage inductive coupling.