H03F3/16

Radio-frequency transmitter and amplifier
09838047 · 2017-12-05 · ·

A method is provided for reducing non-linear effects in an electronic circuit including an amplifier. The method may include receiving a modulated signal at an input of the amplifier, the modulated signal comprising a baseband signal modulated by an oscillator frequency. The method may further include substantially attenuating counter-intermodulation in the modulated signal caused by harmonics of the oscillator frequency and the baseband signal by a resonant circuit. In some embodiments, the resonant circuit may include at least one inductive element and one capacitive element coupled to the at least one inductive element, the at least one inductive element and the at least one capacitive element configured to substantially attenuate counter-intermodulation in the modulated signal.

Radio-frequency transmitter and amplifier
09838047 · 2017-12-05 · ·

A method is provided for reducing non-linear effects in an electronic circuit including an amplifier. The method may include receiving a modulated signal at an input of the amplifier, the modulated signal comprising a baseband signal modulated by an oscillator frequency. The method may further include substantially attenuating counter-intermodulation in the modulated signal caused by harmonics of the oscillator frequency and the baseband signal by a resonant circuit. In some embodiments, the resonant circuit may include at least one inductive element and one capacitive element coupled to the at least one inductive element, the at least one inductive element and the at least one capacitive element configured to substantially attenuate counter-intermodulation in the modulated signal.

Compound semiconductor device, method for producing the same, power-supply unit, and high-frequency amplifier
09831310 · 2017-11-28 · ·

A compound semiconductor device includes: a compound semiconductor multilayer structure including a first buffer layer composed of AlN; and a second buffer layer composed of AlGaN and formed above the first buffer layer, wherein the second buffer layer contains carbon, and wherein the concentration of carbon in the second buffer layer increases with increasing distance from a lower surface of the second buffer layer toward an upper surface of the second buffer layer.

Compound semiconductor device, method for producing the same, power-supply unit, and high-frequency amplifier
09831310 · 2017-11-28 · ·

A compound semiconductor device includes: a compound semiconductor multilayer structure including a first buffer layer composed of AlN; and a second buffer layer composed of AlGaN and formed above the first buffer layer, wherein the second buffer layer contains carbon, and wherein the concentration of carbon in the second buffer layer increases with increasing distance from a lower surface of the second buffer layer toward an upper surface of the second buffer layer.

OUTPUT VOLTAGE GLITCH REDUCTION IN TEST SYSTEMS

A clamp circuit comprises an output transistor and a replica transistor coupled as a current minor pair, wherein the replica transistor is scaled in size to the output transistor by a size ratio; a first current source configured to set a current in the replica transistor, wherein the output current is set at a clamped output current value that is a sum of current of the first current source and a scaled value of the current of the first current source determined according to the size ratio; and a register circuit, wherein a register value stored in the register circuit sets the clamped output current value.

OUTPUT VOLTAGE GLITCH REDUCTION IN TEST SYSTEMS

A clamp circuit comprises an output transistor and a replica transistor coupled as a current minor pair, wherein the replica transistor is scaled in size to the output transistor by a size ratio; a first current source configured to set a current in the replica transistor, wherein the output current is set at a clamped output current value that is a sum of current of the first current source and a scaled value of the current of the first current source determined according to the size ratio; and a register circuit, wherein a register value stored in the register circuit sets the clamped output current value.

Signal processing circuit improving linearity of pulse amplitude modulated signal and communication device including the circuit

A circuit for processing an N-level pulse amplitude modulation (PAM-N) signal according to an embodiment of the present invention comprises: an input unit receiving an input signal; a main amplifier connected to the input unit to amplify the input signal with a first gain; and an output unit outputting an output signal of the main amplifier, and the circuit further comprises an auxiliary amplifier connected in parallel with the main amplifier between the input unit and the output unit to variably amplify at least a portion of the input signal and apply the signal to the output unit according to a linearity improvement control signal corresponding to the output signal.

Signal processing circuit improving linearity of pulse amplitude modulated signal and communication device including the circuit

A circuit for processing an N-level pulse amplitude modulation (PAM-N) signal according to an embodiment of the present invention comprises: an input unit receiving an input signal; a main amplifier connected to the input unit to amplify the input signal with a first gain; and an output unit outputting an output signal of the main amplifier, and the circuit further comprises an auxiliary amplifier connected in parallel with the main amplifier between the input unit and the output unit to variably amplify at least a portion of the input signal and apply the signal to the output unit according to a linearity improvement control signal corresponding to the output signal.

CIRCUIT

A circuit comprising: an input terminal; a first amplifier coupled to the input terminal of the circuit to receive an input signal; a first inductor having a first terminal coupled to the input terminal and a second terminal configured to be coupled to the ground terminal, wherein the first inductor is arranged with a second inductor and configured to magnetically couple therewith, wherein said second inductor is coupled to the first amplifier and is configured to sense a current through the amplifier.

DC offset cancellation circuit and DC offset cancellation method

A DC offset cancellation circuit and a DC offset cancellation method are disclosed. The DC offset cancellation circuit comprises a high-speed amplifier, a voltage comparator, a microprocessor, and a digital-to-analog converter. The high-speed amplifier comprises an input stage with a DC offset cancellation function, an amplification stage, and an output buffer stage. The voltage comparator is connected to the output buffer stage. The microprocessor is connected to the voltage comparator. The digital-to-analog converter is connected to the microprocessor. The digital-to-analog converter is connected to the input stage.