A bias circuit of a power amplifier includes a first part circuit, a second part circuit and a power supply, in which the power supply is connected with a power supply end of the first part circuit; two ends of the first part circuit are connected in parallel with two ends of the second part circuit, and after parallel connection one end of a parallel circuit is connected with a gate of the first transistor of the power amplifier in a signal amplification circuit; the first part circuit is configured to provide a first bias voltage, and the second part circuit is configured to provide a second bias voltage; the two bias voltages are superimposed to provide a stable bias voltage; and an impedance of the bias circuit is in a preset range of the impedance.

Voltage ripple reduction in a power management circuit is disclosed. The power management circuit includes a power amplifier circuit configured to amplify a radio frequency (RF) signal based on a modulated voltage and an envelope tracking integrated circuit (ETIC) configured to provide the modulated voltage to the power amplifier circuit via a conductive path. Notably, an output impedance presenting at an input of the power amplifier circuit can interact with a modulated load current in the power amplifier circuit to create a voltage ripple in the modulated voltage to potentially cause an undesirable error in the RF signal. Herein, the ETIC is configured to modify the modulated voltage based on feedback of the voltage ripple in the modulated voltage. As such, it is possible to reduce the output impedance at the input of the power amplifier circuit to thereby reduce the voltage ripple in the modulated voltage.

Voltage ripple reduction in a power management circuit is disclosed. The power management circuit includes a power amplifier circuit configured to amplify a radio frequency (RF) signal based on a modulated voltage and an envelope tracking integrated circuit (ETIC) configured to provide the modulated voltage to the power amplifier circuit via a conductive path. Notably, an output impedance presenting at an input of the power amplifier circuit can interact with a modulated load current in the power amplifier circuit to create a voltage ripple in the modulated voltage to potentially cause an undesirable error in the RF signal. Herein, the ETIC is configured to modify the modulated voltage based on feedback of the voltage ripple in the modulated voltage. As such, it is possible to reduce the output impedance at the input of the power amplifier circuit to thereby reduce the voltage ripple in the modulated voltage.

Apparatus and methods for a multiclass, broadband, no-load-modulation power amplifier are described. The power amplifier (500) may include a main amplifier (532) operating in a first amplification class and a plurality of peaking amplifiers (536, 537, 538) operating in a second amplification class. The main amplifier (532) and peaking amplifiers (536, 537, 538) may operate in parallel on portions of signals derived from an input signal to be amplified. The main amplifier (532) may see no modulation of its load impedance between a fully-on state of the power amplifier (all amplifiers amplifying) and a fully backed-off state (peaking amplifiers idle). By avoiding load modulation, the power amplifier (500) can exhibit improved bandwidth and efficiency compared to conventional Doherty amplifiers.

A Doherty amplifier includes: a first amplifier to amplify a first signal as an auxiliary amplifier in a case where a frequency of each of the first signal and a second signal is a first frequency, and amplify the first signal as a main amplifier in a case where the frequency of each of the first signal and the second signal is a second frequency; a second amplifier to amplify the second signal as a main amplifier in a case where the frequency of each of the first signal and the second signal is the first frequency, and amplify the second signal as an auxiliary amplifier in a case where the frequency of each of the first signal and the second signal is the second frequency; and a combiner to synthesize the first signal amplified by the first amplifier and the second signal amplified by the second amplifier.

A transceiver is configured for a calibration mode of operation in which an impedance of a transmit chain is tuned responsive to a power measurement of a mixed RF calibration signal to form a tuned transmit chain. A direct conversion mixes an RF calibration signal with a DC offset signal to form the mixed calibration signal. During a normal mode of operation, a heterodyne mixer mixes an LO signal with an IF signal to produce an RF signal that is amplified through the tuned transmit chain.

A radio frequency module includes a module substrate; a power amplifier disposed on or over the module substrate, amplifies a radio frequency signal, and outputs the amplified radio frequency signal as the first transmission signal; a power amplifier disposed on or over the module substrate, amplifies a radio frequency signal, and outputs the amplified radio frequency signal as the second transmission signal; a temperature sensor disposed on or over the module substrate; and a PA control circuit disposed on or over the module substrate and controls amplification operations of the power amplifiers according to a measurement value of the temperature sensor. The maximum output power of the power amplifier is greater than the maximum output power of the power amplifier, and the distance between the temperature sensor and the power amplifier is less than or equal to the distance between the temperature sensor and the power amplifier.

A calibration system comprises an actuator circuit comprising a first delay circuit that receives a plurality of data pulses and a second delay circuit that receives the pulses, wherein one of the first and second delay circuits delays the data pulses independently of the other of the first and second delay circuits; a data switch that receives an output of the actuator circuit including delay data signals of the data pulses from the first and second delay circuits and switches and outputs a plurality of local oscillator (LO) signals for output as a controlled LO signal according to control signals of the delay data signals and applied to the data switch. At least one calibration switch receives the output of the actuator circuit and the plurality of LO+ and LO− signals, and outputs a second controlled LO signal output to a sense circuit.

A filter circuit comprises in a signal line a band filter (BF) allowing to let pass a useful frequency band and a notch filter (NF) circuited in series to the band filter for filtering out a stop band frequency. The notch filter comprises a series circuit of a number of parallel shunt elements (SE1 . . . SE6) wherein each shunt element is shifted infrequency against the other shunt elements that the frequencies thereof are distributed (f1 . . . F6) over a notch band. All shunt elements may be realized as a SAW one-port resonator (TR.sub.NF) including regions with different pitches.

A system may include a first IQ modulator configured to: based on an I and a Q, produce a zero to ninety degree variable phase shifted output signal that changes relative to an input envelope of an RF drive waveform of the RF drive. The system may include a first amplifier path configured to: output a first phase modulated signal. The system may include a second IQ modulator configured to: based on the I and the −Q, produce a zero to negative ninety degree variable phase shifted output signal that changes relative to the input envelope. The system may include a second amplifier path configured to: output a second phase modulated signal, wherein the second phase modulated signal is complementary to the first phase modulated signal. The system may include a vector generator configured to: generate the Q and the −Q for the first and second IQ modulators, respectively.