Methods and devices addressing design of reconfigurable wideband LNAs to meet stringent gain, noise figure, and linearity requirements with multiple gain modes are disclosed. The disclosed teachings can be used to reconfigure RF receiver front-end to operate in various applications imposing stringent and conflicting requirements, such as 5G NR radios. Wideband and narrowband input and output matching with gain modes using a combination of the same hardware and a switching network are also disclosed.

A multi-stage device includes multiple stages such as a first stage and a second stage. During operation, the first stage receives an input signal and outputs an intermediate signal based on the input signal. The second stage is coupled to the first stage to receive the intermediate signal and produce an output signal. According to one configuration, the second stage includes: i) a transistor, and ii) a circuit path between the first stage and the transistor. The transistor component is controlled to derive the output signal from the intermediate signal inputted to the circuit path.

A top-plate sampling analog-to-digital converter (ADC) circuit includes a first ADC stage and a residue amplifier coupled to the first ADC stage. The residue amplifier comprises a first transistor with a control terminal, a first current terminal, and a second current terminal. The residue amplifier also comprises a second transistor with a control terminal, a first current terminal, and a second current terminal. The residue amplifier also comprises a linearity adjustment circuit coupled to a second current terminal of at least one of the first transistor and the second transistor. The linearity adjustment circuit comprises at least one switch that changes its state as a function of an input sampling phase and a gain phase of the residue amplifier.

A measurement circuit may include a transistor having a first terminal, a second terminal, and a third terminal, wherein the first terminal is coupled to a first reference voltage. The measurement circuit may further include a first operational amplifier including a first input coupled to the second terminal of the transistor and an output coupled to the third terminal of the transistor. The first operational amplifier may further include a second input configured to receive a second reference voltage. The measurement circuit may also include a first unity-gain voltage follower including a second operational amplifier having a first input coupled to the first input of the first operational amplifier. Methods of measuring a threshold voltage, semiconductor devices, and electronic systems are also described.

A top-plate sampling analog-to-digital converter (ADC) circuit includes a first ADC stage and a residue amplifier coupled to the first ADC stage. The residue amplifier comprises a first transistor with a control terminal, a first current terminal, and a second current terminal. The residue amplifier also comprises a second transistor with a control terminal, a first current terminal, and a second current terminal. The residue amplifier also comprises a linearity adjustment circuit coupled to a second current terminal of at least one of the first transistor and the second transistor. The linearity adjustment circuit comprises at least one switch that changes its state as a function of an input sampling phase and a gain phase of the residue amplifier.

An electronic circuit comprises an input stage, a gain stage operatively coupled to the input stage, a primary output stage operatively coupled to the gain stage, a replica output stage operatively coupled to the gain stage in parallel to the primary output stage, and a clock circuit. The clock circuit operates the electronic circuit in multiple phases including a sampling phase to disconnect the primary output stage and the replica output stage from the gain stage to obtain an offset voltage, an active phase to reconnect the primary output stage to apply the offset voltage to reduce an offset at the primary output stage, and an intermediate phase to first reconnect the replica output stage to the gain stage prior to the active phase.

A (pre) driver circuit includes first and second output terminals configured to be coupled to a power transistor. A differential stage has non-inverting and inverting inputs for receiving an input voltage. The input voltage is replicated as an output voltage across the first and second output terminals as a drive signal for the power transistor. The differential stage includes a differential transconductance amplifier in a voltage follower arrangement configured to provide continuous regulation of a voltage at the first output terminal with respect to the second output terminal.

The invention aims for a polarisation circuit of a power component comprising a capacitive dividing bridge and a resistive dividing bridge formed on the same substrate as the component. An additional electrode 1 in the front face 100 of the substrate makes it possible to adjust one of the capacitance values of the capacitive dividing bridge according to the other of the capacitance values coming from one of the electrodes of the power component. The sizing of this additional electrode furthermore makes it possible to obtain a leakage resistance contributing to the resistive dividing bridge.

Alternatively, two additional resistances R, R formed in the front face of the substrate making it possible to obtain the resistive dividing bridge independently of the capacitive dividing bridge.

A wide band communications circuit buffer can include a pair of NPN bipolar transistor emitter followers deployed as a voltage buffer and disposed at inputs before and outputs after an equalization module, and a pair of diode connected NPN transistors deployed as a level shifter and disposed following the emitter followers before an output of the wide band driver to keep an output level at the output of the wide band buffer close to a desired level. Resistors connected between emitters and a V.sub.EE terminal can be used to further adjust the DC level. An LC tank filter can be provided between emitters of the voltage buffer components and the circuit's outputs to pass and boost high frequency signals provided to next stage components. The wide band buffer is, inter alia, appropriate for use in providing a DC level shift function as used in wired data communication systems circuitry.

An electronic circuit comprises an input stage, a gain stage operatively coupled to the input stage, a primary output stage operatively coupled to the gain stage, a replica output stage operatively coupled to the gain stage in parallel to the primary output stage, and a clock circuit. The clock circuit operates the electronic circuit in multiple phases including a sampling phase to disconnect the primary output stage and the replica output stage from the gain stage to obtain an offset voltage, an active phase to reconnect the primary output stage to apply the offset voltage to reduce an offset at the primary output stage, and an intermediate phase to first reconnect the replica output stage to the gain stage prior to the active phase.