A reactance cancelling radio frequency (RF) circuit array is disclosed. The reactance cancelling RF circuit array includes multiple RF circuits each coupled to one or two adjacent RF circuits by one or two pairs of coupling mediums each having a respective length less than one-quarter wavelength. In one aspect, an RF input signal is first split across the RF circuits and then combined to form an RF output signal. As a result, each RF circuit requires a lower power handling capability to process a portion of the RF input signal. In another aspect, each pair of the coupling mediums can cause reactance cancellation in each reactance-cancelling pair of the RF circuits. By coupling the RF circuits via the coupling mediums and enabling splitting-combining among the RF circuits, it is possible to miniaturize the reactance cancelling RF circuit array for improved performance across a wide frequency spectrum.

A power combiner circuit comprises a network topology for broadband RF and microwave systems that includes coupling elements, internodal matching sections, and an output matching section. The network topology serves as a combining mechanism for power from multiple power amplifiers. The network topology is designed so that characteristic impedances of transmissions lines serving as the coupling elements, internodal matching sections, and an output matching section produce a load impedance at an output port that is matched to the impedances seen by each power amplifier providing power to the power combiner circuit. Such a network topology is scalable to an unlimited number of power amplifiers, and enables a desired broadband frequency response for power amplification, while realizing a very low level of power output loss between input and output ports.

The present disclosure relates to the field of amplifier circuits (driver amplifiers) for electro-optical modulators, in particular for amplifying an electrical signal for driving electro-optical modulators, an amplifier circuit is proposed for amplifying a signal comprising a gain amplifier, a distributed amplifier, a resistor, and a current source, wherein the input of the distributed amplifier is electrically connected to the output of the gain amplifier; the resistor terminates the input of the distributed amplifier; and the current source is electrically connected in parallel to the resistor. A method of setting a bias voltage of such an amplifier circuit is also proposed. Furthermore, a transmitter, in particular an optical transmitter, comprising such an amplifier circuit and a system comprising such a transmitter and a signal source are also proposed.

In a distributed amplifier, a plurality of cascode amplifiers connected in parallel between an input side transmission line and an output side transmission line are provided, a transmission line is connected to an input terminal of an output transistor of each of the amplifiers, and a bias potential is applied from a bias circuit to the input terminal of the output transistor via the transmission line.

Distributed amplifiers with controllable linearization are provided herein. In certain embodiments, a distributed amplifier includes a differential input transmission line, a differential output transmission line, and a plurality of differential distributed amplifier stages connected between the differential input transmission line and the differential output transmission line at different points or nodes. The distributed amplifier further includes a differential non-linearity cancellation stage connected between the differential input transmission line and the differential output transmission line and providing signal inversion relative to the differential distributed amplifier stages. The differential non-linearity cancellation stage operates with a separately controllable bias from the differential distributed amplifier stages, thereby providing a mechanism to control the linearity of the distributed amplifier.

An apparatus for high-power combining includes multiple power-combining building blocks, a passive input network to couple one or more input signals to one or more input ports of the multiple power-combining building blocks, and a passive output network to couple to output ports of the multiple power-combining building blocks and to generate one or more amplified output signals. Each power-combining building block includes M high-power amplifiers (HPAs) coupled in parallel to a respective passive input network and a respective passive output network. A count of the multiple power-combining building blocks is determined based on a desired total number N of the HPAs and a number M of the HPAs in each power-combining building block.

A power combiner circuit comprises a network topology for broadband RF and microwave systems that includes coupling elements, internodal matching sections, and an output matching section. The network topology serves as a combining mechanism for power from multiple power amplifiers. The network topology is designed so that characteristic impedances of transmissions lines serving as the coupling elements, internodal matching sections, and an output matching section produce a load impedance at an output port that is matched to the impedances seen by each power amplifier providing power to the power combiner circuit. Such a network topology is scalable to an unlimited number of power amplifiers, and enables a desired broadband frequency response for power amplification, while realizing a very low level of power output loss between input and output ports.

A power combiner circuit comprises a network topology for broadband RF and microwave systems that includes coupling elements, internodal matching sections, and an output matching section. The network topology serves as a combining mechanism for power from multiple power amplifiers. The network topology is designed so that characteristic impedances of transmissions lines serving as the coupling elements, internodal matching sections, and an output matching section produce a load impedance at an output port that is matched to the impedances seen by each power amplifier providing power to the power combiner circuit. Such a network topology is scalable to an unlimited number of power amplifiers, and enables a desired broadband frequency response for power amplification, while realizing a very low level of power output loss between input and output ports.

An envelope tracking (ET) circuit is provided. In examples discussed herein, the ET circuit can be configured to operate in a fifth-generation (5G) standalone (SA) mode and a 5G non-standalone (NSA) mode. In the SA mode, the ET circuit can enable a first pair of ET power amplifier circuits to amplify a 5G signal based on ET for concurrent transmission in a 5G band(s). In the NSA mode, the ET circuit can enable a second pair of ET power amplifier circuits to amplify an anchor signal and a 5G signal based on ET for concurrent transmission in an anchor band(s) and a 5G band(s), respectively. As such, the ET circuit may be provided in a 5G-enabled wireless communication device (e.g., a 5G-enabled smartphone) to help improve power amplifier linearity and efficiency in both 5G SA and NSA networks.

An amplifier circuit for compensating an output signal provided at an output of the amplifier circuit comprises a cascade of sub-amplifiers. Each sub-amplifier of the cascade contributes to a respective part of the output signal. The cascade of sub-amplifiers comprises an end sub-amplifier and at least one preliminary sub-amplifier. At least one error correction block is coupled to apply feedforward error correction to an output of one of the at least one preliminary sub-amplifier.