Methods and architectures for closed loop digital pre-distortion (DPD) in a multi-stream phased array communication system include sampling outputs, from transmit antennas or dedicated analog detectors, of a plurality of RF power amplifiers operating in transmission of multi-stream transmission, correcting or normalizing the detected outputs, summing the outputs into a combined DPD feedback signal and selecting pre-distortion vectors to be used in altering the output of the PAs.

There has been a problem that linearity is degraded in the conventional amplifier when the idle current is reduced in order to lower the power consumption. An amplifier of the present invention includes: a bias circuit to cause a bias current to flow; an amplifying element to amplify a signal by causing an output current corresponding to the bias current to flow; a bias current subtracting circuit to detect the signal and subtract, from the bias current, a current based on an amplitude of the signal detected; and a bias current adding circuit having an operation starting point higher than an operation starting point of the bias current subtracting circuit, and to detect the signal and add, to the bias current, a current based on an amplitude of the signal detected.

An apparatus of a transmitter and method are provided, the apparatus comprising a processor that calculates a supply voltage (SV) value (SVV) to provide as an SV for a power amplifier (PA) of the transmitter for transmissions during a transmission time slot (TS). When the SV<an envelope tracking (ET) threshold (ETT), then the processor configures the PA to transmit a signal in an average power tracking (APT) mode that maintains the SV at the SVV during the TS. When the SVETT, and an APT condition is met, then the processor configures the PA to transmit the signal in the APT mode. When the SVETT, and the APT condition is not met, then the processor transmits by an adjustment to the SVV to track an amplitude modulation envelope during the TS in an ET mode.

An envelope tracking (ET) amplifier circuit is provided. The ET amplifier circuit includes an amplifier circuit configured to amplify a radio frequency (RF) signal based on an ET modulated voltage. The ET modulated voltage corresponds to a time-variant voltage envelope, which can be misaligned from a time-variant signal envelope of the RF signal due to inherent temporal delay in the ET amplifier circuit. As a result, the amplifier circuit may suffer degraded linearity performance. In this regard, a voltage processing circuit is provided in the ET amplifier circuit and configured to operate in a low-bandwidth mode and a high-bandwidth mode. In the high-bandwidth mode, the voltage processing circuit is configured to cause the ET modulated voltage to be modified to help improve delay tolerance of the ET amplifier circuit. As a result, it may be possible to reduce linearity degradation of the amplifier circuit to a predetermined threshold.

Variable gain amplifiers (VGA) with output phase invariance are provided herein. In certain embodiments, a VGA is operable in a selected gain setting chosen from multiple gain settings that provide different amounts of amplification to a radio frequency (RF) input signal. The VGA includes a gain transistor that has a substantially constant bias current across the gain settings, such that the VGA's output phase, input impedance matching, and/or input return loss are substantially constant. The gain setting of the VGA is selected by controlling relative biasing of a pair of cascode transistors each connected to the gain transistor by a corresponding degeneration resistor. The degeneration resistors provide compensation that reduces or eliminates a difference in output phase of the VGA across gain settings, for instance, by introducing a zero in a transfer function of the VGA that cancels a pole arising from the cascode transistors.

A gain modulation circuit includes a load circuit, a differential circuit, a current source, a resistor, a first transistor, and a detector circuit. The load circuit is configured to receive a supply voltage. The differential circuit is coupled to the load circuit. The differential circuit and the load circuit are configured to generate a pair of output voltages according to a pair of input voltages and the supply voltage. The current source is coupled to the differential circuit. The resistor is coupled to the differential circuit and the current source. The first transistor is coupled to the differential circuit. The detector circuit is configured to generate a detection signal according to the pair of input voltages. A turned-on degree of the first transistor is adjusted based on the detection signal, to adjust a linear region of the gain modulation circuit.

An envelope tracking (ET) circuit and related power amplifier apparatus is provided. An ET power amplifier apparatus includes an ET circuit and a number of amplifier circuits. The ET circuit is configured to provide a number of ET modulated voltages to the amplifier circuits for amplifying concurrently a number of radio frequency (RF) signals. The ET circuit includes a target voltage circuit for generating a number of ET target voltages adapted to respective power levels of the RF signals and/or respective impedances seen by the amplifier circuits, a supply voltage circuit for generating a number of constant voltages, and an ET voltage circuit for generating the ET modulated voltages based on the ET target voltages and a selected one of the constant voltages. By employing a single ET circuit, it may be possible to reduce footprint and improve heat dissipation of the ET power amplifier apparatus.

A wireless communication system includes a power amplifier (PA) configured to receive a radio frequency (RF) input signal and to produce a PA output signal, the PA output signal being an amplified version of the RF input signal. A sensor subsystem is configured to perform asynchronous statistical sampling of the RF input signal and of the PA output signal and to generate a sensor subsystem output. A controller, in communication with the sensor subsystem, is configured to obtain the sensor subsystem output and to infer performance of the PA, and may control one or more of a plurality of internal PA parameters. The controller may include a neural network processor to associate a particular statistical input/output characterization with a particular inferred performance for the PA. Compared to known approaches, the system is scalable and achieves lower power consumption, and is configured to obtain information about linearity performance.

A system has a plurality of non-linear circuit stages and an intervening linear circuit stage. An input signal is provided to a first non-linear circuit stage, and from the first non-linear circuit stage, to the linear circuit stage. The first non-linear circuit stage applies a second-order distortion to the input signal and provides the resulting signal to the linear circuit stage. The resulting signal that is output from the linear circuit stage is inverted with respect to the input signal and suitably linearly processed (attenuated or amplified). This signal is then provided to a second non-linear circuit that applies a second-order distortion and outputs a signal that has an overall reduction in second-order distortion.

System and method for integrating an input signal to generate an output signal. The system includes a first integrator configured to receive the input signal and generate an integrated signal based on at least information associated with the input signal, a second integrator configured to receive the integrated signal and generate the output signal based on at least information associated with the integrated signal, and a compensation capacitor coupled to the first integrator and the second integrator. The first integrator includes a first integration capacitor and a first operational amplifier including a first input terminal and a first output terminal, the first integration capacitor being coupled between the first input terminal and the first output terminal. The second integrator includes a second integration capacitor and a second operational amplifier including a second input terminal and a second output terminal.