An amplifying circuit includes a first reconfigurable amplifier configured to selectively operate in a cascode mode or a non-cascode mode, wherein an input of the first reconfigurable amplifier is coupled to a first input of the amplifying circuit, and an output of the first reconfigurable amplifier is coupled to an output of the amplifying circuit. The amplifying circuit also includes a second reconfigurable amplifier configured to selectively operate in the cascode mode or the non-cascode mode, wherein an input of the second reconfigurable amplifier is coupled to a second input of the amplifying circuit, and an output of the second reconfigurable amplifier is coupled to the output of the amplifying circuit.

An inverting amplifier includes an input terminal, an output terminal, a PMOS transistor, another PMOS transistor, an NMOS transistor, another NMOS transistor, and a clamp circuit. The PMOS transistors are connected in series between a supply voltage and an output terminal. The NMOS transistors are connected in series between a ground voltage and the output terminal. The clamp circuit is connected to the gate of the other PMOS transistor and the gate of the other NMOS transistor. The clamp circuit includes a switch, a capacitor, another switch, and another capacitor. At least one of the gate of the PMOS transistor and the gate of the NMOS transistor is connected to the input terminal.

An amplification device includes an amplification stage having a transconductance amplification transistor and an output terminal. A biasing circuit is configured to bias in common mode the output terminal to a bias potential obtained on the basis of a voltage present between the gate and the source of the amplification transistor, and to compensate for parasitic variations of the voltage present between the gate and the source of the amplification transistor.

A linear amplifier is provided to have higher efficiency for an envelope tracking modulator. In one embodiment, a first stage amplifier circuit can be simply operated in a high gain mode or a high bandwidth mode for different applications, without using large chip area. In another embodiment, an output stage has a cascode structure whose dynamic range is controlled according to a voltage level of a supply voltage, to make a core device within the output stage have better protection and suitable dynamic range.

An amplifier circuit including a substrate layer and a plurality of lateral bipolar junction transistors positioned entirely above the substrate. The lateral bipolar junction transistors include a plurality of monolithic emitter-collector regions coplanar to each other. Each of the emitter-collector regions is both an emitter region of a first bipolar junction transistor a collector region of a second bipolar junction transistor from the lateral bipolar junction transistors. Accordingly, the lateral bipolar junction transistors are electrically coupled in series circuit at the emitter-collector regions.

A driver for a piezo actuator includes a transconductance amplifier to produce an output current, a slew rate-controlled amplifier, and a logic gate. The logic gate receives a first control signal to cause the transconductance amplifier to transition to a high impedance mode, receive a compare signal indicative of the amplitude of the output current produced by the transconductance amplifier being less than a threshold, and generate a second control signal to the transconductance amplifier responsive to the first control signal indicating the high impedance mode for the transconductance amplifier and the compare signal indicative of the output current being less than the threshold. A voltage is provided to the slew rate-controlled amplifier upon assertion of the first control signal, wherein the voltage causes the slew rate controlled amplifier to generate a voltage to the transconductance amplifier that causes the transconductance amplifier's output to fall below the threshold.

A driver for a piezo actuator includes a transconductance amplifier to produce an output current, a slew rate-controlled amplifier, and a logic gate. The logic gate receives a first control signal to cause the transconductance amplifier to transition to a high impedance mode, receive a compare signal indicative of the amplitude of the output current produced by the transconductance amplifier being less than a threshold, and generate a second control signal to the transconductance amplifier responsive to the first control signal indicating the high impedance mode for the transconductance amplifier and the compare signal indicative of the output current being less than the threshold. A voltage is provided to the slew rate-controlled amplifier upon assertion of the first control signal, wherein the voltage causes the slew rate controlled amplifier to generate a voltage to the transconductance amplifier that causes the transconductance amplifier's output to fall below the threshold.

An amplification device includes an amplification stage having a transconductance amplification transistor and an output terminal. A biasing circuit is configured to bias in common mode the output terminal to a bias potential obtained on the basis of a voltage present between the gate and the source of the amplification transistor, and to compensate for parasitic variations of the voltage present between the gate and the source of the amplification transistor.

An amplifier includes a differential amplification block suitable for receiving and amplifying a first differential input signal and a second differential input signal; an output block suitable for determining an output signal according to a state of amplified signals outputted from the differential amplification block; and an output range restriction block suitable for controlling an output range of the output signal outputted from the output block based on a maximum clamping signal and a minimum clamping signal.

Techniques are disclosed to allow for a switched capacitor digital power amplifier (PA) that operates using high supply voltage levels beyond twice the maximum voltage rating for any of the transistor terminals such as Vds/Vdg/Vsg.