A biocompatible recording system includes a number of input channels for acquiring electronic information from the neural system of a living being. The recording system includes a preamplifier and further amplifier stages. An input of a second amplifier stage is coupled to an output of the preamplifier. A low-pass filter having a capacitance multiplier is connected to the second amplifier stage. The preamplifier of the recording system is designed using P-MOS technology.

An amplifier includes an amplifying stage, a cascoded circuit, an input feed-forward circuit and an output stage. The amplifying stage is arranged receiving a differential input pair to generate an amplified differential input pair. The input feed-forward circuit is coupled to the cascoded circuit, and is arranged for feeding the differential input pair forward to the cascoded circuit. The output stage is coupled to the amplifying stage and the cascoded circuit, and is arranged for generating a differential output pair according to the amplified differential input pair and an output of the cascoded circuit.

A semiconductor device having a first differential amplification circuit is disclosed. The first differential amplification circuit includes a first input transistor having a gate configured to receive a first signal, a second input transistor having a gate configured to receive a second signal, a first current source connected to a source of the first input transistor and a source of the second input transistor, a first transistor that is connected in parallel to the source of the first input transistor and the source of the second input transistor and has a gate configured to receive the first signal, and a second transistor that is connected in series to the first transistor and has a gate configured to receive a control signal.

A differential amplifier comprises a first differential circuitry structure including a first part comprising at least one branch of transistors and a second part comprising at least one branch of transistors, and a second circuitry structure. The second cicuitry structure has a first non-linear device and a second non-linear device. The non-linear devices each comprise a transistor having a control node connected to a differential output terminals of the differential amplifier. A common centre node of the non-linear devices is connected to a control node of one of the transistors of each branch of the first part having a differential output terminal. Amplifier applications, communication devices and network nodes are also disclosed.

An amplifier including a first cascode circuit including a first transistor and a second transistor whose source or emitter is coupled to a drain or a collector of the first transistor, a second cascode circuit being a differential pair with the first cascode circuit, the second cascode circuit including a third transistor whose source or emitter is coupled to a source or an emitter of the first transistor and a fourth transistor whose source or emitter is coupled to a drain or collector of the third transistor, a first feedback path that couples between an output terminal of the third transistor and an input terminal of the first transistor, the first feedback path including a first capacitative element, and a second feedback path that couples between an output terminal of the first transistor and an input terminal of the third transistor, the second feedback path including a second capacitative element.

An amplifier for a receiver circuit is disclosed. The amplifier has an input node (V.sub.in) and an output node (V.sub.out). It comprises a tunable tank circuit connected to the output node (V.sub.out), a feedback circuit path connected between the output node (V.sub.out) and the input node (V.sub.in), and a tunable capacitor connected between an internal node of the feedback circuit path and a reference-voltage node. A receiver circuit and a communication apparatus is disclosed as well.

A transistor cell can be modeled as a transistor with a collector, a base, and an emitter operating with a current at the collector to produce a minimum transconductance in the transistor cell that increases a current gain and improves at least one operating characteristic of the transistor cell. The operating characteristics include bandwidth, gain, and output power.

An amplifying circuit includes a reference voltage generating circuit, a common-mode voltage conversion circuit, a common-mode negative feedback circuit, and an amplifying sub-circuit. The reference voltage generating circuit generates a first reference voltage, a second reference voltage, and a reference common-mode voltage according to a post-stage common-mode voltage. The common-mode voltage conversion circuit converts the pre-stage output differential signal into a differential input signal according to the reference common-mode voltage. The common-mode negative feedback circuit generates a control voltage to quickly establish a common-mode negative feedback of the amplifying sub-circuit, wherein the first reference voltage and the second reference voltage are used to cancel a baseline signal of the pre-stage output differential signal. The amplifying circuit can eliminate the baseline signal, convert the common-mode voltage and quickly establish the common-mode negative feedback.

Certain aspects of the present disclosure generally relate to electronic circuits and, more particularly, to an operational transconductance amplifier (OTA). One example amplifier generally includes: a first pair of input transistors; a first pair of cascode transistors coupled in cascode with the first pair of input transistors, respectively; a second pair of input transistors; a second pair of cascode transistors coupled in cascode with the second pair of input transistors, respectively; and a third pair of input transistors coupled to the second pair of cascode transistors, respectively.

Described are an amplifier circuits, systems, and methods for amplifying a plurality of sinusoid signals having a relative phase difference to each other. The amplifier circuit comprises a first sequence of at least three transistor amplifiers, wherein a first terminal of each transistor amplifier of the first sequence is configured to receive one respective signal of the plurality sinusoid signals. The amplifier further comprises a second sequence of at least three transistor amplifiers. A second terminal of each transistor amplifier of the second sequence is connected to a third terminal of one respective transistor amplifier of the first sequence. A first terminal of each transistor amplifier of the second sequence is connected to the third terminal of a next transistor amplifier of the second sequence. The first terminal of a last transistor amplifier is connected to the third terminal of a first transistor amplifier.