Provided are a transmitting device connected to a receiving device via a channel and the receiving device connected to the transmitting device via a channel. The transmitting device connected to a receiving device includes: a transmitter connected to the channel via an output node and configured to transmit, via the channel, a transmission signal to the receiving device, the transmitter having a transmission impedance associated therewith that is variable; and a monitoring device configured to detect a channel impedance of the channel and a receiving impedance of the receiving device by monitoring a voltage level of the output node, the monitoring device configured to set the transmission impedance based on the channel impedance and the receiving impedance.

The present disclosure relates to an offset elimination operation of an internal operational amplifier of a data driving circuit and relates to a technique that applies different offset elimination methods for each position of an operational amplifier.

An apparatus includes a first amplifier, a second amplifier, and a compensation-setting generator to generate a first amplifier compensation setting and second amplifier compensation setting. A controller is operable to: i) apply the first amplifier compensation setting to the first amplifier and apply the second amplifier compensation setting to the second amplifier. The controller is further operable to switch between generating updates to the first amplifier compensation setting and the second amplifier compensation setting.

A voltage regulator and a power supply are provided. The voltage regulator includes an operational amplifier and an offset voltage control module. The operational amplifier includes an input terminal and an output terminal, and is configured to generate an output voltage to be output from the output terminal based on a reference voltage received from the input terminal. The offset voltage control module includes one stage of regulation branch or more stages of regulation branches connected in parallel, and is configured to control an offset voltage of the operational amplifier based on selection of the regulation branch to regulate the output voltage. Since sine each stage of regulation branch in the offset voltage control module is based on a transistor structure, as compared with the voltage dividing resistor in the related art, the transistor has lower power consumption, and thus power consumption of the voltage regulator is lowered.

An analog circuit including a pair of input nodes and a pair of output nodes is coupled to a mismatch reduction circuit including an input node, an output node, a phase controller that times even and odd phases, an input switch, and an output switch. The input switch electrically connects the mismatch reduction circuit input node to a first node of the pair of analog circuit input nodes during each even phase and to electrically connects the mismatch reduction circuit input node to a second node of the pair of analog circuit input nodes during each odd phase. The output switch electrically connects a first node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each even phase and electrically connects a second node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each odd phase.

A data converter including an autozeroing circuit including a plurality of gain circuits having a first amplification circuit and a first capacitor connected to the first amplification circuit, the first amplification circuit performing a switch feedthrough offset cancellation operation of storing an offset voltage of the autozeroing circuit in the capacitor through a switch, a comparator circuit including a first input terminal and a second input terminal, the comparator circuit comparing a first input terminal voltage level of the first input terminal with a second input terminal voltage level of the second input terminal, a first switch unit connected between the autozeroing circuit and the comparator circuit, the first switch disconnecting the autozeroing circuit from the comparator circuit during the switch feedthrough offset cancellation operation of the autozeroing circuit, and a second switch unit connected between a first input signal line and a second input signal line.

A programmable gain amplifier may include: (a) a differential amplifier having first and second input terminals and first and second output terminals, the differential amplifier providing an output signal of the programmable gain amplifier across the first and second output terminals of the differential amplifier; (b) a first set of one or more resistors coupling the first output terminal of the differential amplifier to the first input terminal of the differential amplifier; (c) a second set of one or more resistors coupling the first input terminal of the differential amplifier to a first input terminal of the programmable gain amplifier; and (d) a first set of one or more switches each connected in parallel with one or more resistors in the first or second set of resistors. The first set of switches may include two or more individually programmable switches. Each of the switches may be implemented by an input-signal independent switch disclosed herein.

An amplifier circuit can include an amplifier and a resistor network coupled to the amplifier. The resistor network can include a range resistor coupled in parallel to a resistor string, and one or more switches coupled to the resistor string. The resistor network can be used to calibrate gain and common mode rejection ratio (CMRR) of the amplifier circuit.

An amplifier comprising a differential amplifier configured to be provide a comparator function, and a gain trimming circuit is electrically configured to provide gain trimming using a T-network comprising a varistor element. In addition, a method of trimming the gain of a differential amplifier, comprising the steps of a first step, (a) providing the differential amplifier comprising resistors in both of its paths, a second step, (b) providing a varistor in a T-network between both said paths; and lastly, a third step, (c) trimming the gain of the differential amplifier by adjusting the varistor's resistance.

A fully balanced differential difference amplifier includes a first differential input stage that receives an input voltage and a second differential input stage that receives a common-mode voltage. A first resistive-degeneration group is coupled to the first differential input and a second resistive-degeneration group is coupled to the second differential input. A differential output stage generates an output voltage. A first switch is coupled in parallel to the first resistive-degeneration group and a second switch is coupled in parallel with the second resistive-degeneration group. The first and second switches are driven into the closed state when the voltage input assumes a first value such that said first input stage operates in the linear region, and are driven into the open state when the voltage input assumes a second value, higher than the first value, such that the first input stage operates in a non-linear region.