A programmable gain amplifier may include: (a) a differential amplifier having first and second input terminals and first and second output terminals, the differential amplifier providing an output signal of the programmable gain amplifier across the first and second output terminals of the differential amplifier; (b) a first set of one or more resistors coupling the first output terminal of the differential amplifier to the first input terminal of the differential amplifier; (c) a second set of one or more resistors coupling the first input terminal of the differential amplifier to a first input terminal of the programmable gain amplifier; and (d) a first set of one or more switches each connected in parallel with one or more resistors in the first or second set of resistors. The first set of switches may include two or more individually programmable switches. Each of the switches may be implemented by an input-signal independent switch disclosed herein.

An electronic circuit for amplifying signals with two components in phase quadrature, which includes: a feedback amplifier with a feedback capacitor; a switch that drives charging and discharging of the feedback capacitor; an additional capacitor; and a coupling circuit, which alternatively connects the additional capacitor in parallel to the feedback capacitor or else decouples the additional capacitor from the feedback capacitor. The switch opens at a first instant, where a first one of the two components assumes a first zero value; the coupling circuit decouples the additional capacitor from the feedback capacitor in a way synchronous with a second instant, where the first component assumes a second zero value.

An analog circuit including a pair of input nodes and a pair of output nodes is coupled to a mismatch reduction circuit including an input node, an output node, a phase controller that times even and odd phases, an input switch, and an output switch. The input switch electrically connects the mismatch reduction circuit input node to a first node of the pair of analog circuit input nodes during each even phase and to electrically connects the mismatch reduction circuit input node to a second node of the pair of analog circuit input nodes during each odd phase. The output switch electrically connects a first node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each even phase and electrically connects a second node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each odd phase.

An analog circuit including a pair of input nodes and a pair of output nodes is coupled to a mismatch reduction circuit including an input node, an output node, a phase controller that times even and odd phases, an input switch, and an output switch. The input switch electrically connects the mismatch reduction circuit input node to a first node of the pair of analog circuit input nodes during each even phase and to electrically connects the mismatch reduction circuit input node to a second node of the pair of analog circuit input nodes during each odd phase. The output switch electrically connects a first node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each even phase and electrically connects a second node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each odd phase.

An analog circuit including a pair of input nodes and a pair of output nodes is coupled to a mismatch reduction circuit including an input node, an output node, a phase controller that times even and odd phases, an input switch, and an output switch. The input switch electrically connects the mismatch reduction circuit input node to a first node of the pair of analog circuit input nodes during each even phase and to electrically connects the mismatch reduction circuit input node to a second node of the pair of analog circuit input nodes during each odd phase. The output switch electrically connects a first node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each even phase and electrically connects a second node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each odd phase.

A method includes providing a first voltage to a first output node during a first time interval, providing a second voltage to the first output node during a second time interval, and averaging the first and second voltages to provide a reference voltage to a second output node. The first voltage includes a proportional-to-absolute-temperature (PTAT) component, a complementary-to-absolute-temperature (CTAT) component, and a first residual offset component. The second voltage includes the PTAT component, the CTAT component, and a second residual offset component. An apparatus includes a discrete-time circuit to provide the first voltage to the first output node during the first time interval and to provide the second voltage to the first output node during the second time interval, and a filter to average the first and second voltages to provide the reference voltage to the second output node.

A device includes an amplifier and calibration circuitry coupled to the amplifier. The calibration circuitry is configured to receive calibration values. The calibration circuitry is also configured to generate an output value in response to receiving a timing input.

Broadly speaking, embodiments of the present techniques provide an amplification circuit comprising a sense amplifier and at least one Correlated Electron Switch (CES) configured to provide a signal to the sense amplifier. The sense amplifier outputs an amplified version of the input signal depending on the signal provided by the CES element. The signal provided by the CES element depends on the state of the CES material. The CES element provides a stable impedance to the sense amplifier, which may improve the reliability of reading data from the bit line, and reduce the number of errors introduced during the reading.

A programmable amplifier includes an amplifier, an input capacitor, a feedback circuit, and a high-pass filter circuit. The amplifier has an input coupled to the input capacitor for receiving an input signal. The feedback circuit includes multiple feedback capacitors of differing capacitance values that are each selectively coupled between the output of the amplifier and the input of the amplifier using multiple first switches. The high-pass filter circuit includes multiple switched capacitors of differing capacitance values that are each selectively coupled between the amplifier output and a ground node using multiple second switches. The first switches are configured to be selectively switched on for activating at least one feedback capacitor to adjust a gain of the amplifier, while the second switches are configured to be selectively switched at a first and second phase of a clock signal to adjust a high-pass cutoff frequency of the amplifier independently of how the gain is adjusted.

A semiconductor device includes an operational transconductance amplifier (OTA) with a matched pair of transistors including a first transistor and a second transistor, and configuration units that include a first set of switches, a second set of switches, and an input transistor. Gain adjustment circuitry is coupled to adjust gain of the OTA. Measurement circuitry is coupled to measure offset in the OTA. Control logic is configured to operate the first and second sets of switches to couple input transistors of a first group of the configuration units to the first transistor of the matched pair of transistors, and to couple input transistors of a remaining group of the configuration units to the second transistor of the matched pair of transistors. Settings of the first and second sets of switches are selected to minimize the offset.