A calibration apparatus is used for calibrating characteristics of a power amplifier (PA) in a transmitter. The calibration apparatus includes an adaptive bias generator circuit that is used to track an envelope of an input signal received by control terminals of transistors of the PA and generate an adaptive bias voltage to the control terminals of the input transistors in response to the envelope of the input signal.

Described is an apparatus which comprises: an amplifier to receive a reference voltage; and calibration logic which is operable to receive a first voltage and to provide the reference voltage to the amplifier, wherein the calibration logic is operable to generate a look-up table (LUT) that maps the first voltage to a drive current.

An amplifier circuit includes: an amplifier; a first switched resistor unit configured by connecting in series a first resistance element having one or more resistors and a first switch, and having one end connected to an input terminal of the amplifier; a second resistance element unit connected between an other end of the first switched resistor unit and an output terminal of the amplifier and including one or more resistors; a second switch connected between a common connection point of the first switched resistor unit and the second resistance element unit and a reset potential point; and a control circuit for exclusively turning on and off the first switch and the second switch, respectively.

Various embodiments of the present technology may comprise methods and apparatus for driver calibration. The methods and apparatus may comprise various circuits and/or systems to minimize an offset output current (e.g., a drive current) due to an offset voltage in an operational amplifier. The methods and apparatus may comprise a current comparator circuit and a replica circuit that operate in conjunction with each other to monitor the drive current and provide a feedback signal, which is then used to adjust the drive current and improve the accuracy of the drive current.

An apparatus for calibrating a differential circuit that includes a differential integrator having an input, a gain, and an output connected to a comparator. The differential integrator output is chargeable to a threshold prior to an integration period. The differential integrator integrates the input during the integration period such that the differential integrator output goes toward zero from the threshold. The comparator detects the output of the differential integrator reaching zero. The apparatus includes a closed-loop gain trim circuit to perform a coarse calibration to adjust and set the gain of the differential integrator and a reference generator that generates the threshold to which the differential integrator output is pre-charged. The reference generator is trimmable during a fine calibration to adjust and set the threshold to correct for residual gain error in the differential circuit remaining after the coarse calibration is performed.

A comparator offset calibration system having a comparator offset evaluator and a switched-capacitor network is disclosed, which is in an analog and digital dual domain structure. The comparator offset evaluator receives digital data from an analog-to-digital conversion module, evaluates an offset of a comparator of the analog-to-digital conversion module based on the received digital data, and outputs an evaluated result. The switched-capacitor network processes the evaluated result to generate a control signal. The analog-to-digital conversion module adjusts the offset of the comparator according to the control signal.

A current feed-back instrumentation amplifier (CFIA) comprises a differential pair with degeneration for amplifying small differential voltages in the presence of large common-mode voltages. The CFIA includes input and feedback transconductors and a chopping modulator circuit that continuously swaps tail current sources between the transconductors. This tail current swapping reduces the contribution to the CFIA's gain error caused by random mismatch between the tail currents of the input and feedback transconductors. The modulator circuit operates on a clock cycle to periodically swap the tail current sources. As a result, even if the tail currents are mismatched, on average the tail currents (transconductor gains) will approximately equal out, and the contribution of the tail current difference to the gain error is canceled out.

A current feed-back instrumentation amplifier (CFIA) comprises a differential pair with degeneration for amplifying small differential voltages in the presence of large common-mode voltages. The CFIA includes input and feedback transconductors and a trimming circuit that trims the back-bias voltages of the transistors in each transconductor. The trimming circuit includes a plurality of selectable resistors disposed in the signal path of the tail current in each transconductor. Each of the plurality of selectable resistors has a switch coupled to it. When a switch is closed, only the resistors up to the respective switch are in the signal path of the bulk-to-source voltage of the differentially paired transistors. The resistor trimming circuit reduces the mismatch between transconductances of the respective differential pair transistors, in turn reducing mismatch of the overall transconductances of the transconductors, and thereby reducing the CFIA's gain error.

A method for calculating a calibration gain used for common-mode rejection in a current sensing system may include measuring a first value of a common-mode voltage associated with the current sensing system and a first output value of the current sensing system occurring at the first value of the common-mode voltage, measuring a second value of the common-mode voltage associated with the current sensing system and a second output value of the current sensing system occurring at the second value of the common-mode voltage, and based on a difference between the second output value of the current sensing system and the first output value of the current sensing system and a difference between the second value of the common-mode voltage and the first value of the common-mode voltage, calculating the calibration gain.

An amplifier circuit arrangement and a method for calibrating the same. In an embodiment an amplifier circuit arrangement includes a desired signal path including a differential amplifier for an analog signal having an input side and an output side and an analog-to-digital converter having an output terminal, a first feedback path to calibrate an offset of the desired signal path coupled to differential signal lines at the output side of the differential amplifier and to differential signal lines at the input side of the differential amplifier, the first feedback path including a comparator and at least one counter controlled by an output of the comparator and a second feedback path to calibrate a drift of the desired signal path coupled to the output terminal of the analog-to-digital converter and to the differential signal lines at the input side of the differential amplifier, the second feedback path including an average filter.