An oscilloscope probe includes a tip network, a low-loss signal cable, and a terminating assembly. The tip network is connected to the signal cable and is configured to electrically connect to a device under test via a tip network node. The terminating assembly includes an amplifier, a feedback network and a terminating attenuator. The amplifier has an inverting input, a non-inverting input connected to ground, and an amplifier output configured to connect to an oscilloscope input. The feedback network is connected between the inverting input and the amplifier output. The terminating attenuator includes a first loop circuit and a second loop circuit. The first loop circuit is provided between the signal cable and the inverting input of the amplifier. The second loop circuit is provided between the signal cable, and ground. Resistance of terminating resistors in the loop circuits are selected to match characteristic impedance of the signal cable.

In described examples, a circuit includes a first current mirror circuit. The first current mirror circuit is coupled to a power input terminal. A first stage is coupled to the first current mirror circuit, and a second stage is coupled to the first stage and to the first current mirror circuit. An amplifier is coupled to the first and second stages. The amplifier has first and second input terminals. The first input terminal is coupled to the first stage, and the second input terminal is coupled to the second stage. A second current mirror circuit is coupled to the first stage, the second stage and the amplifier.

An amplification apparatus includes an amplifier having an inverting terminal, and a non-inverting terminal connected to a reset voltage node, a first capacitor connected to the inverting terminal, an input voltage being applied to the first capacitor, a second capacitor connected to the inverting terminal and an output terminal of the amplifier, and a duty-cycled resistor, connected in parallel to the second capacitor, including a first resistor. The duty-cycled resistor is configured to connect the first resistor and the inverting terminal and to disconnect the first resistor and the reset voltage node during a first time interval included in a period to complete an on-and-off cycle of the duty-cycled resistor, and disconnect the first resistor and the inverting terminal and to connect the first resistor and the reset voltage node during a second time interval included in the period.

An operational amplifier integrated circuit includes a differential pair of transistors having a first input, a second input. A bias current generator applies a bias current to an output of the differential pair of transistors. A control loop generates a control voltage arising from a difference in potentials between the first input and the second input. An additional current that is added to the bias current is generated in response to the control voltage.

In an embodiment an integration circuit has a first input terminal configured to receive a first input signal, a second input terminal configured to receive a second input signal, an output terminal to provide an output signal as a function of the first and the second input signal, a first and a second amplifier, each being switchably connected between the first or the second input terminal and the output terminal, and a capacitor which is switchably coupled in a feedback loop either of the first or of the second amplifier such that the capacitor and one of the first and the second amplifier form an inverting integrator providing the output signal. Therein the integration circuit is prepared to be operated in a first and a second subphase, wherein in each of first and second subphases one of the first and the second input signals is supplied to the inverting integrator and the respective other one of first and the second input signals is supplied to the respective other one of the first and the second amplifier.

An output buffer circuit for avoiding voltage overshoot includes an input stage, an output bias circuit, an output stage, a clamp circuit, and a control unit. The input stage includes a positive input terminal, for receiving an input voltage, and a negative input terminal. The input stage generates a current signal according to the input voltage. The output bias circuit is coupled to the input stage, for generating a dynamic bias according to the current signal. The output stage is coupled to the input stage and the output bias circuit, including an output terminal, reversely coupled to the positive input terminal, and at least one output transistor, coupled to the output bias circuit and the output terminal, for providing a driving current to the output terminal according to the dynamic bias to generate an output voltage.

A circuit and method in an amplifier circuit for filtering a DC offset in differential input signals and inserting a programmable adjustable crosspoint offset in differential output signals. An amplifier circuit includes a differential amplifier circuit configured to amplify differential input signals into differential output signal. The amplifier circuit further includes a feedback circuit coupled between the differential output signals and the differential input signals. The feedback circuit is configured to generate a programmably adjustable crosspoint offset in the differential output signal and a programmably adjustable cutoff frequency of the feedback circuit. An amplifier method includes amplifying differential input signals into differential output signals, generating a programmably adjustable crosspoint offset in the differential output signal, and generating a programmably adjustable cutoff frequency of a feedback circuit between the differential output signals and the differential input signals.

The present disclosure relates to a signal acquisition device, a signal acquisition method and a wearable apparatus. A preamplifier circuit in the signal acquisition device amplifies an obtained sEMG signal to produce an amplified sEMG signal. A baseline drift suppression circuit in the signal acquisition device extracts a first low-frequency component from the amplified sEMG signal and performs subtraction processing between the amplified sEMG signal and the first low-frequency component to obtain a difference signal. A filter circuit in the signal acquisition device filters the difference signal to obtain a target acquisition signal. With introduction of baseline drift suppression in the signal acquisition circuit, the baseline drift caused by a low-frequency component in a sEMG signal is eliminated, and the stability of a target acquisition signal is enhanced.

In some embodiments, a circuit for use in devices involving digital-to-analog conversion of signals includes: a capacitive digital-to-analog converter array and an amplifier. The capacitive digital-to-analog converter includes an input port for receiving a digital input signal and an output port. The amplifier includes capacitive feedback loops that include a first capacitor coupling the output of the amplifier with the input of the amplifier and a second capacitor coupled to the output port of the digital-to-analog converter array at the input of the amplifier. The circuit further includes a set of switches that include a first switch and a second switch coupled with opposed ends of the second capacitor at the input and at the output of the amplifier, respectively.

An amplifier assembly (100) includes an amplifier (102) having an input terminal, an output terminal and a feedback terminal; a first feedback path connecting the output terminal to the feedback terminal; a second feedback path connecting the output terminal to the feedback terminal; a switch (124) positioned in the second feedback path, the switch (124) opening or closing in response to a voltage at the output terminal relative to a breakpoint, when the switch (124) is open, the amplifier assembly (100) has a first gain and when the switch (124) is closed, the amplifier assembly (100) has a second gain; and a thermally variable element (152) connected to the switch (124), the thermally variable element (152) configured to generate a compensation voltage to maintain the breakpoint in response to varying temperature of the switch (152).