The present disclosure relates to a semiconductor device and a cell potential measuring apparatus capable of amplifying and reading a potential of solution with high accuracy. A reading electrode reads the potential of the solution. A differential amplifier includes a current mirror circuit. The reading electrode is connected to a first input terminal of the differential amplifier which is connected to a gate of a first input transistor connected to a diode-connected pMOS transistor of the current mirror circuit. An output terminal of the differential amplifier is connected to a second input terminal of the differential amplifier, which is connected to a gate of a second input transistor connected to a pMOS transistor of the current mirror circuit which is not diode-connected, via a capacitor. For example, the present disclosure is applied to the cell potential measuring apparatus and the like.

A switched capacitor circuit includes a first main sampler circuit, a second main sampler circuit, a first replica sampler circuit, and a second replica sampler circuit. The first main sampler circuit samples a first input of a differential input, and generates a first output corresponding to the sampled first input based on a first reference voltage. The second main sampler circuit samples a second input of the differential input, and generates a second output corresponding to the sampled second input based on a second reference voltage. The first replica sampler circuit receives the first input, and holds the received first input based on the second reference voltage. The second replica sampler circuit receives the second input, and holds the received second input based on the first reference voltage.

A circuit for generating differential reference voltages, a circuit for detecting a signal peak, and an electronic device. In the circuit for generating reference voltages, a common-mode extraction circuit receives a first differential signal and a second differential signal, extracts a common-mode level from the first differential signal and the second differential signal, and applies the common-mode level to a non-inverting input terminal of a first operational amplifier. The first operational amplifier, a main control switch, a first voltage dividing resistor, a second voltage dividing resistor, and a first direct current power source constitute a feedback loop, to generate differential reference voltages matching with the common-mode level. Adjusting a current provided by the first direct current power source can change the differential reference voltages, obtaining a reference for to-be-detected amplitude of the signals. Signal amplitude is detected with high precision, and detection reliability of a peak detecting circuit is improved.

A ramp generator includes an integrator including a first stage having first and second inputs and first and second outputs, and a second stage including first and second transistors coupled between a power supply rail and ground. A node between the first and second transistors is coupled to the output of the integrator amplifier. A control terminal of the first transistor is coupled to the first output of the first stage, and a control terminal of the second transistor is coupled to the second output of the first stage. A first current flows from the output to ground during a ramp event in the ramp signal generated from the output. Trimming circuitry is coupled to the output of the integrator amplifier to provide a second current to the output of the integrator amplifier in response to trimming inputs. The second current substantially matches the first current.

A calibration circuit configured to calibrate a signal of a sensing unit comprises: an amplifier, a first impedance element and a second impedance element. The amplifier has a first input terminal, a second input terminal and an output terminal. The first input terminal is coupled to a first terminal of the sensing unit, the second input terminal is coupled to a reference voltage, and the output terminal is feedback to the first input terminal and outputs the readout signal. A first terminal of the first impedance element is coupled to the first input terminal of the amplifier, and a second terminal of the first impedance element is coupled to a calibration voltage. A first terminal of the second impedance element is coupled to the first terminal of the first impedance element, and a second terminal of the second impedance element is coupled to the output terminal of the amplifier.

An operational amplifier includes a gain boost circuit. The gain boost circuit includes a first differential gm amplifier of a first stage, and a second differential gm amplifier of a post stage. Phase compensation capacitors are provided between inputs and outputs of a system of the second differential gm amplifier.

A pseudo-resistor structure, comprises: a first and a second PMOS transistor or PN diode configured as two-terminal devices, wherein the positive terminal of the first PMOS transistor or PN diode is connected to the positive terminal of the second PMOS transistor or PN diode, and wherein the negative terminal of the first PMOS transistor or PN diode is connected to an input (A) of the pseudo-resistor structure and wherein the negative terminal of the second PMOS transistor or PN diode is connected to an output (C) of the pseudo-resistor structure, and a dummy transistor or dummy diode connected to the input (A), wherein the dummy transistor or dummy diode is further connected to a bias voltage for compensating a leakage current through the first and the second PMOS transistors or PN diodes. A closed-loop operational amplifier circuit comprising the pseudo-resistor structure is provided. Also, a bio-potential sensor comprising the closed-loop operational amplifier circuit is provided.

A gain amplifier of a sensing circuit for sensing degradation of an OLED display panel, the gain amplifier comprising: an operation amplifier; and a plurality of gain amplifier cells sequentially coupled to the operation amplifier. Each of the gain amplifier cells comprises a plurality of capacitors each placed between two internal nodes of the gain amplifier cell, excluding a ground node, such that a voltage gain of the gain amplifier and a DC offset of the gain amplifier are determined according to capacitances of the capacitors without considering parasitic capacitance.

A current integrator includes an operational amplifier, an integration capacitor and an offset cancelation capacitor. The operational amplifier includes a first input stage and a second input stage. The first input stage is coupled to an input terminal of the current integrator. The integration capacitor is coupled between the first input stage of the operational amplifier and an output terminal of the current integrator. The offset cancelation capacitor is coupled to the second input stage of the operational amplifier.

Described herein are systems and methods that reduce settling time in amplifier circuits, such as voltage sense amplifiers (VSA) or current sense amplifiers (CSA) circuits, that comprise a feedback path. When the feedback path is interrupted via a switch, a CSA circuit switches to open loop. A sample-and-hold circuit holds the output voltage of the amplifier, such that when a load is connected to the CSA circuit, the open loop settling time, which is shorter than the closed loop settling time, is allowed to pass before the CSA output voltage is measured, thereby, advantageously preventing any potential disturbance present at the CSA output from being fed back to the CSA input.