The present invention is directed to electrical circuits and techniques thereof. More specifically, embodiments of the present invention provide a differential amplifier that has a differential amplifier section, a current source, and a feedback section. The differential amplifier section comprises NMOS transistors that receives two voltage inputs and generate a differential output. The current source provides a long tail for the differential amplifier section. The feedback section generates a feedback voltage based on a reference bias voltage. The feedback voltage is used by an amplifier to control the current source and to keep the biasing and gain of the differential amplifier substantially constant. There are other embodiments as well.

An apparatus, including: a buffer configured to receive an input differential signal and generate an output signal based on the input differential signal, wherein the buffer includes a first buffer stage including: a first field effect transistor (FET); a second FET coupled in series with the first FET between a first voltage rail and a second voltage rail; a third FET; a fourth FET coupled in series with the third FET between the first voltage rail and the second voltage rail, wherein the first and third FETs include gates coupled together, and wherein the second and fourth FETs include gates configured to receive positive and negative components of the input differential signal; and a first capacitor coupled between a drain of the second FET and the gates of the first and third FETs.

Described herein is a preamplifier circuit for a capacitive acoustic transducer provided with a MEMS detection structure that generates a capacitive variation as a function of an acoustic signal to be detected, starting from a capacitance at rest; the preamplifier circuit is provided with an amplification stage that generates a differential output signal correlated to the capacitive variation. In particular, the amplification stage is an input stage of the preamplifier circuit and has a fully differential amplifier having a first differential input (INP) directly connected to the MEMS detection structure and a second differential input (INN) connected to a reference capacitive element, which has a value of capacitance equal to the capacitance at rest of the MEMS detection structure and fixed with respect to the acoustic signal to be detected; the fully differential amplifier amplifies the capacitive variation and generates the differential output signal.

An operational amplifying circuit are provided. The operational amplifying circuit includes a control circuit, pull-up and pull-down transistors, first and second bias circuits, and a bias voltage generating circuit. The control circuit includes first and second input terminals, and is configured to change, when an input voltage transitions to a first level, a voltage level of a pull-up node and a pull-down node to a second level different from the first level. The pull-up transistor provides a power supply voltage to the output terminal. The pull-down transistor connects the output terminal to a ground voltage. The first bias circuit provides a first bias current to the control circuit. The bias voltage generating circuit generates a bias voltage when the voltage level of at least one of the pull-up and pull-down nodes reaches a threshold voltage level, and the second bias circuit provides a second bias current to the control circuit.

Described herein are a method and an apparatus for minimizing within-die variations in performance parameters of a processor. The apparatus comprising: a reference generator to generate an adjustable compensated reference signal; a bias generator to generate a bias signal based on the adjustable compensated reference signal; a transmitter coupled with the bias generator to transmit an output signal; and a feedback mechanism to sample the output signal from the transmitter and to provide the sampled output signal to the bias generator.

A switched-capacitor circuit comprising a differential operational amplifier and a feedback circuit is described. In some embodiments, the feedback circuit may be configured to provide a reference voltage that is insensitive to temperature and/or process variations. In some embodiments, the feedback circuit may be configured to mitigate the time delay associated with one or more capacitors of the switched-capacitor circuit. The switched-capacitor circuit may be controlled by a pair of control signals. During a first phase, one or more capacitors may be charged, or discharged, through an input signal. During a second phase, the electric charge of the one or more capacitors may be retained.

A current source with hysteresis for an output circuit includes a tail current transistor, a resistor and a differential pair. The tail current transistor is used for supplying a current to the output circuit. The resistor is coupled to a drain terminal of the tail current transistor. The differential pair, coupled to the resistor, is used for controlling a magnitude of the current supplied to the output circuit. The differential pair includes a first transistor, of which a bulk terminal is coupled to a terminal of the resistor; and a second transistor, of which a bulk terminal is coupled to another terminal of the resistor.

A differential input stage includes first and second input transistors with current flow paths are coupled between a tail transistor current flow path and first and second nodes, respectively. An output stage includes first and second output transistors having current flow paths between a supply line and first and second output nodes, respectively, coupled to the first and second nodes. First and second common-mode control transistors have current flow paths jointly coupled to a ground current flow path of a common-mode tail transistor. The first common-mode control transistor has a control terminal resistively coupled to the first and second output nodes. A bias duplicate transistor has a current flow path arranged in a bias current flow line between the supply line and ground. The bias duplicate transistor is coupled in a 1:N current mirror arrangement with the tail transistor in the differential input stage.