Embodiments relate to systems, methods, and computer-readable media to enable design and creation of receiver circuitry. One embodiment is a receiver apparatus comprising a plurality of receiver arrangements, each receiver arrangement having a sampling circuit and a multi-stage differential amplifier connected to the sampling circuit. Each receiver arrangement is configurable via switches between an amplifying mode and an autozero mode. Control circuitry may select output data from a sampling circuit of one or more receiver arrangements that are not in autozero mode. In various embodiments, settings for individual receiver arrangements may be set based on decision feedback equalization (DFE).

The disclosure provides an amplifier. The amplifier includes a first transistor that receives a first input and generates a first load current. A first output node is coupled to a power supply through a first load resistor. The first load resistor receives the first load current. A first capacitor network is coupled to the first output node and draws a first capacitive current from the first output node. A first current buffer is coupled between the first output node and the first transistor. A current through the first current buffer is a summation of the first load current and the first capacitive current.

The disclosure provides an amplifier. The amplifier includes a first transistor that receives a first input and generates a first load current. A first output node is coupled to a power supply through a first load resistor. The first load resistor receives the first load current. A first capacitor network is coupled to the first output node and draws a first capacitive current from the first output node. A first current buffer is coupled between the first output node and the first transistor. A current through the first current buffer is a summation of the first load current and the first capacitive current.

A signal transceiver includes a signal transmitter driving a first differential link between a supply voltage of the signal transmitter and a fraction of the supply voltage, and driving a second differential link between the faction of the supply voltage and a reference ground. The signal transceiver also includes a signal receiver in which the first differential link is coupled to a gate node of an NMOS transistor and to a source node of a PMOS transistor; and the second differential link is coupled to a source node of the NMOS transistor and to a gate node of the PMOS transistor.

The present invention provides a class AB amplifier, wherein the class AB amplifier includes a cascode stage with a filter and an output stage. The cascode stage with the filter is arranged for receiving an input signal to generate a first driving signal and a second driving signal, wherein the filter filters the input signal to generate an filtered input signal, and at least one of the first driving signal and the second driving signal is generated according to the filtered input signal. The output stage is coupled to the cascode stage, and is arranged for generating an output signal according to the first driving signal and the second driving signal.

Embodiments relate to systems, methods, and computer-readable media to enable design and creation of receiver circuitry. One embodiment is a receiver apparatus comprising a plurality of receiver arrangements, each receiver arrangement having a sampling circuit and a multi-stage differential amplifier connected to the sampling circuit. Each receiver arrangement is configurable via switches between an amplifying mode and an autozero mode. Control circuitry may select output data from receiver arrangements that are not in autozero mode using multiplexer circuitry. In various embodiments, settings for individual receiver arrangements may be set based on decision feedback equalization (DFE).

A power amplifier circuit includes lower-stage and upper-stage differential amplifying pairs, a combiner, first and second inductors, and first and second capacitors. First and second signals are input into the lower-stage differential amplifying pair. The upper-stage differential amplifying pair outputs first and second amplified signals. The combiner combines the first and second amplified signals. The lower-stage differential amplifying pair includes first and second transistors. A supply voltage is supplied to the collectors of the first and second transistors. The first and second signals are supplied to the bases of the first and second transistors. The upper-stage differential amplifying pair includes third and fourth transistors. A supply voltage is supplied to the collectors of the third and fourth transistors. The emitters of the third and fourth transistors are grounded via the first and second inductors and are connected to the first and second transistors via the first and second capacitors.

The present disclosure relates to an offset elimination operation of an internal operational amplifier of a data driving circuit and relates to a technique that applies different offset elimination methods for each position of an operational amplifier.

An integrated circuit includes a first high-pass filter having an input coupled to receive a first signal and an output coupled to a first input of a first differential pair of transistors. A second high-pass filter includes an input coupled to receive a second signal and an output coupled to a second input of the first differential pair of transistors. The second signal may be a complementary signal of the first signal. A second differential pair of transistors includes control electrodes coupled to a first voltage supply terminal. A boost circuit is coupled between the second differential pair of transistors and the first voltage supply terminal. A low-pass filter is coupled between the first differential pair of transistors and the second differential pair of transistors.

An RF receiver includes a low-noise amplifier (LNA) to receive and amplify RF signals, a transformer-based IQ generator circuit, one or more load resisters, one or more mixer circuit, and a downconverter. The transformer-based IQ generator is to generate a differential in-phase local oscillator (LOI) signal and a differential quadrature (LOQ) signal based on a local oscillator (LO) signal received from an LO. The load resisters are coupled to an output of the transformer-based IQ generator. Each of the load resisters is to couple one of the differential LOI and LOQ signals to a predetermined bias voltage. The mixers are coupled to the LNA and the transformer-based IQ generator to receive and mix the RF signals amplified by the LNA with the differential LOI and LOQ signals to generate an in-phase RF (RFI) signal and a quadrature RF (RFQ) signal. The downconverter is to down convert the RFI signal and the RFQ signal into IF signals.