A wireless receiving device is provided. The wireless receiving device includes a first passive mixer and a common gate amplifier. The first passive mixer receives an oscillation signal. The common gate amplifier is coupled to the first passive mixer, and automatically adjusts the input impedance of the common gate amplifier according to the oscillation frequency of the oscillation signal.

A wireless receiving device is provided. The wireless receiving device includes a first passive mixer and a common gate amplifier. The first passive mixer receives an oscillation signal. The common gate amplifier is coupled to the first passive mixer, and automatically adjusts the input impedance of the common gate amplifier according to the oscillation frequency of the oscillation signal.

Methods, systems, and devices for differential amplifier schemes for sensing memory cells are described. In one example, a memory apparatus may include a differential amplifier having a first input node configured to be coupled with a memory cell and having an output node configured to be coupled with a sense component. In some examples, the memory apparatus may also include a capacitor having a first node coupled with the first input node, and a first switching component configured to selectively couple a second node of the capacitor with the output node. The differential amplifier may configured such that a current at the output node is proportional to a difference between a voltage at the first input node of the differential amplifier and a voltage at the second input node of the differential amplifier.

An illustrative embodiment of an integrated circuit configured for galvanically isolated signaling includes a transfer conductor carrying a modulated carrier signal. A floating transfer loop is electromagnetically coupled to the transfer conductor to receive the modulated carrier signal. The floating transfer loop includes a primary of a step-up transformer. A receiver is coupled to a secondary of the step-up transformer to receive the modulated carrier signal in an amplified, differential fashion, and to demodulate the modulated carrier signal to obtain a digital receive signal.

A receiver includes a passive CTLE (continuous-time linear equalizer) configured to receive a first voltage signal from a first node and output a current signal to a second node in accordance with a first control signal; a CG (common-gate) amplifier configured to receive the current signal and output a second voltage signal at a third node in accordance with a second control signal; a first active inductor configured to provide an inductive load at the third node; a CS (common-source) CTLE configured to receive the second voltage signal and output a third voltage signal at a fourth node in accordance with a third control signal; a second active inductor configured to provide an inductive load at the fourth node; and a decision circuit configured to receive the third voltage signal and output a decision in accordance with a clock signal.

An active device and circuits utilized therewith are disclosed. In an aspect, the active device comprises an n-type transistor having a drain, gate and bulk and a p-type transistor having a drain, gate and bulk. The n-type transistor and the p-type transistor include a common source. The device includes a first capacitor coupled between the gate of the n-type transistor and the gate of the p-type transistor, a second capacitor coupled between the drain of the n-type transistor and the drain of p-type transistor and a third capacitor coupled between the bulk of the n-type transistor and the bulk of p-type transistor. The active device has a high breakdown voltage, is memory less and traps even harmonic signals.

Circuitry for voltage-to-current conversion, and in particular to differential voltage-to-current conversion circuitry. Such circuitry is operable to receive a differential voltage input signal and output a corresponding differential current signal. First and second controllable current sinks are connected to first and second load nodes of the circuitry so as to draw corresponding sink currents from those nodes.

Methods, systems, and devices for differential amplifier schemes for sensing memory cells are described. In one example, a memory apparatus may include a differential amplifier having a first input node configured to be coupled with a memory cell and having an output node configured to be coupled with a sense component. In some examples, the memory apparatus may also include a capacitor having a first node coupled with the first input node, and a first switching component configured to selectively couple a second node of the capacitor with the output node. The differential amplifier may configured such that a current at the output node is proportional to a difference between a voltage at the first input node of the differential amplifier and a voltage at the second input node of the differential amplifier.

The disclosure relates to technology for an apparatus having a current conveyer comprising a first stage having a first differential input, and a second stage having a second differential input. The first and second stages are configured to operate in a push-pull mode to provide an output signal at a current conveyer output between the first stage and the second stage. The apparatus has a first frequency mixer configured to generate a first mixer signal based on an input signal and an oscillator signal having a first frequency. The first frequency mixer is configured to provide the first mixer signal to the first differential input. The apparatus has a second frequency mixer configured to generate a second mixer signal based on the input signal and a second oscillator signal having the first frequency. The second frequency mixer is configured to provide the second mixer signal to the second differential input.

An apparatus, including a positive input for an input differential signal; a negative input for the input differential signal; a positive output for an output differential signal; a negative output for the output differential signal; a first capacitor including a first terminal coupled to the positive output; a second capacitor including a first terminal coupled to the negative output; and a switching network configured to: couple a second terminal of the first capacitor to the negative input or a positive node based on a mode signal; and couple a second terminal of the second capacitor to the positive input or a negative node based on the mode signal.