Embodiments are directed to a buffer circuit that includes a first circuit and a second circuit. The first and second circuits include sets of transistors along pairs of related signal paths, each of the transistors being driven in response to two related input signals having different but related phases. The first circuit generates a first related output signal in response to one of the pairs of related signal paths and the second circuit generates a second output signal in response to another of the pairs of related signal paths. The first and second circuits provide a linear transfer function across one of the first and one of the second sets of transistors via one of the first pair and second pair of related signal paths.

Amplifier configuration for load-line enhancement is described herein. In some implementations, an apparatus includes an amplifier. The amplifier includes at least one plus transistor stack, at least one minus transistor stack, and at least one inductor. The at least one plus transistor stack is coupled to a plus amplifier node and a plus input node. The at least one minus transistor stack is coupled to a minus amplifier node and a minus input node. The at least one inductor is coupled between the plus amplifier node and the minus amplifier node, with the at least one inductor including an inter-inductor node. The amplifier also includes a minus power switch coupled between the minus amplifier node and one or more supply voltages and an inductor power switch coupled between the inter-inductor node and at least one supply voltage.

A power amplifier circuit includes lower-stage and upper-stage differential amplifying pairs, a combiner, first and second inductors, and first and second capacitors. First and second signals are input into the lower-stage differential amplifying pair. The upper-stage differential amplifying pair outputs first and second amplified signals. The combiner combines the first and second amplified signals. The lower-stage differential amplifying pair includes first and second transistors. A supply voltage is supplied to the collectors of the first and second transistors. The first and second signals are supplied to the bases of the first and second transistors. The upper-stage differential amplifying pair includes third and fourth transistors. A supply voltage is supplied to the collectors of the third and fourth transistors. The emitters of the third and fourth transistors are grounded via the first and second inductors and are connected to the first and second transistors via the first and second capacitors.

There are an amplifier circuit which includes a first current source that is connected to a power supply line to which a first electric potential is supplied, a differential input circuit that is connected between the first current source and a first node and configured to receive a differential input signal, a second current source that is connected between a power supply line to which a second electric potential is supplied and the first node, and a load circuit that is connected between a power supply line to which the first electric potential is supplied and a second node, and an inductor circuit is further connected between the first node and the second node. Thereby, the amplifier circuit achieves both lower voltage and linearity.

An integrated circuit includes a first high-pass filter having an input coupled to receive a first signal and an output coupled to a first input of a first differential pair of transistors. A second high-pass filter includes an input coupled to receive a second signal and an output coupled to a second input of the first differential pair of transistors. The second signal may be a complementary signal of the first signal. A second differential pair of transistors includes control electrodes coupled to a first voltage supply terminal. A boost circuit is coupled between the second differential pair of transistors and the first voltage supply terminal. A low-pass filter is coupled between the first differential pair of transistors and the second differential pair of transistors.

Low noise amplifiers (LNAs) with low noise figure are provided. In certain embodiments, an LNA includes a single-ended LNA stage including an input for receiving a single-ended input signal from an antenna and an output for providing a single-ended amplified signal, a balun for converting the single-ended amplified signal to a differential signal, and a variable gain differential amplification stage for amplifying the differential signal from the balun. Implementing the LNA in this manner provides low noise figure, high gain, flexibility in controlling gain, and less sensitivity to ground/supply impedance.

A stacked amplifier circuit includes an input stage having first and second input ports respectively defined by inputs of first and second transistors. A transformer arrangement includes first and second primary windings and first and second secondary windings. The first secondary winding is connected to an output of the first input transistor and the second secondary winding is connected to an output of the second input transistor. Portions of the magnetic fields generated by the primary windings couple to their respective secondary windings. An output stage is AC coupled to the first and second secondary windings and has an output connected to the first and second primary windings. The input stage and the output stage are arranged in a stacked configuration such that a bias current of the output stage is reused as bias current for the input stage.

Disclosed is a 5G (5.sup.th generation) or pre-5G communication system for supporting a data transmission rate higher than that of a 4G (4.sup.th generation) communication system such as long-term evolution (LTE). A transmission device comprises: a first amplification unit having a common source structure, including cross coupled capacitors, and amplifying an input signal; a second amplification unit, having a common gate structure, for amplifying a signal output from the first amplification unit; and a first removal unit which is connected to output terminals of the first amplification unit and input terminals of the second amplification unit and which removes at least one portion of second harmonics. The first removal unit can offset, with respect to a fundamental frequency, at least some of parasitic capacitance generated from the output terminals of the first amplification unit and the input terminals of the second amplification unit, and can ground a signal having a secondary harmonic frequency with respect to the secondary harmonic frequency.

Techniques for providing a modulation driver signal are disclosed. In an example, a modulation driver can include a first transistor configured to receive a first input signal having a first voltage swing, a second transistor coupled in series with the first transistor, and a third transistor configured to limit a third voltage swing across the second transistor. The second transistor can be configured to provide a representation of the first input signal as a first output signal of the modulator driver. The first output signal can have a second voltage swing greater than the first voltage swing.

Techniques for monitoring a distortion signal of a power amplifier circuit, where the output of a distortion monitoring circuit includes little or no fundamental signal and closely represents the actual distortion of the amplifier circuit of a wired communications system. The power amplifier circuit can generate a distortion feedback signal that does not affect the power amplifier's output power capability, e.g., no inherent loss in the fundamental output of the amplifier. That is, using a distortion monitor circuit, the power amplifier circuit can resolve a distortion feedback signal from the intended output signal of the output power amplifier circuit.