A novel comparison circuit, a novel amplifier circuit, a novel battery control circuit, a novel battery protection circuit, a power storage device, a semiconductor device, an electronic device, and the like are provided. The semiconductor device includes a capacitor, a first amplifier circuit including a first output terminal electrically connected to a first electrode of the capacitor, and a second amplifier circuit including an input terminal, a second output terminal, a first transistor, and a second transistor; a second electrode of the capacitor is electrically connected to the input terminal; the input terminal is electrically connected to a gate of the first transistor and one of a source and a drain of the second transistor; one of a source and a drain of the first transistor is electrically connected to the second output terminal; the second transistor has a function of supplying a potential to the input terminal and holding the potential; and a channel formation region of the second transistor includes a metal oxide containing at least one of indium and gallium.

A MOSFET has a current conduction path between source and drain terminals. A gate terminal of the MOSFET receives an input signal to facilitate current conduction in the current conduction path as a result of a gate-to-source voltage reaching a threshold voltage. A body terminal of the MOSFET is coupled to body voltage control circuitry that is sensitive to the voltage at the gate terminal of the MOSFET. The body voltage control circuitry responds to a reduction in the voltage at the gate terminal of the MOSFET by increasing the body voltage of the MOSFET at the body terminal of the MOSFET. As a result, there is reduction in the threshold voltage. The circuit configuration is applicable to amplifier circuits, comparator circuits and current mirror circuits.

An instrumentation amplifier including a pair of input amplifiers, each including an input transistor and a feedback current amplifier configured to amplify and feedback an error current from the input transistor. The arrangement can enable a current efficient solution where the amplifier can operate with very low input signals that are close to, or potentially below ground, without requiring a negative power supply voltage.

In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.

A MOSFET has a current conduction path between source and drain terminals. A gate terminal of the MOSFET receives an input signal to facilitate current conduction in the current conduction path as a result of a gate-to-source voltage reaching a threshold voltage. A body terminal of the MOSFET is coupled to body voltage control circuitry that is sensitive to the voltage at the gate terminal of the MOSFET. The body voltage control circuitry responds to a reduction in the voltage at the gate terminal of the MOSFET by increasing the body voltage of the MOSFET at the body terminal of the MOSFET. As a result, there is reduction in the threshold voltage. The circuit configuration is applicable to amplifier circuits, comparator circuits and current mirror circuits.

A power amplifier circuitry (100) comprises: a transistor stack (110) comprising at least two stacked transistor units (112A, 112B, 112C) for amplifying input signals; wherein each stacked transistor unit (112A, 112B, 112C) comprises a plurality of controllable segments (120-1 to 120-N, 130-1 to 130-N, 140-1 to 140-N), each comprising a segment transistor (122, 132, 142), wherein source terminals (123, 133, 143) within each transistor unit are connected, drain terminals (125, 135, 145) within each transistor unit are connected and gate terminals (124, 134, 144) within each transistor unit are connected, wherein each segment transistor (122, 132, 142) further comprises a back gate terminal (126, 136, 146) for setting a body bias, wherein at least two of the segment transistors (122, 132, 142) within each transistor unit have independently connected back gate terminals (126, 136, 146); and a control unit (190) configured to control the body bias for selecting an amplifier class of each of the controllable segments (120-1 to 120-N, 130-1 to 130-N, 140-1 to 140-N) of each of the stacked transistor units (112A, 112B, 112C).

A differential amplifier includes first and second MOS transistors of a first conductivity type which constitute a differential input circuit, a bias current source which supplies a bias current to the first and second MOS transistors, and a third MOS transistor of the first conductivity type provided between the bias current source and the first and second MOS transistors and constituted to limit a back-gate voltage of the first and second MOS transistors.

An apparatus has four transistors. The first and third transistors each have a gate coupled to a first input terminal and second input terminal respectively, a source coupled to a current source and to a first terminal of a bias voltage source, and a substrate coupled to a second terminal of the bias voltage source. The second and fourth transistors each have a gate coupled to the first input terminal and the second input terminal respectively, a source coupled to the drain of the first and third transistors respectively, a drain coupled to a lower voltage supply and a substrate coupled to its source. The bias voltage source increases the threshold voltages of the first and third transistors above the second and fourth transistors, respectively. This ensures that the first and third transistors turn on after the second and fourth transistors, respectively.

In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.

A circuit includes a first switch assembly having a first input node and a first output node, and a second switch assembly having a second input node and a second output node. The circuit further includes a third switch assembly an operational amplifier, and a buffer. The third switch assembly has a third input node and a third output node. The third input node is coupled to the second output node, and the third output node is coupled to the first output node. The buffer has a buffer input and a buffer output. The buffer input is coupled to an input stage of the operational amplifier. The buffer output is coupled to the third switch assembly.