Monolithic microwave integrated circuits (MMICs) tolerant to electrical overstress are provided. In certain embodiments, a MMIC includes a signal pad that receives a radio frequency (RF) signal, and an RF circuit coupled to the RF signal pad. The RF circuit includes a transistor layout, an input field-effect transistor (FET) implemented using a first portion of a plurality of gate fingers of the transistor layout, and an embedded protection device electrically connected between a gate and a source of the input FET and implemented using a second portion of the plurality of gate fingers. The MMIC is tolerant to electrical overstress events, such as field-induced charged-device model (FICDM) events.

A compensation circuit of a power amplifier includes a varactor, a voltage sensor and a control circuit. The varactor is coupled to an input terminal of the power amplifier. The voltage sensor is arranged for detecting an amplitude of an input signal of the power amplifier to generate a detecting result. The control circuit is coupled to the varactor and the voltage sensor, and is arranged for controlling a bias voltage of the varactor to adjust a capacitance of the varactor according to the detecting result.

Methods and systems for a pseudo-differential low-noise amplifier at Ku-band may comprise a low-noise amplifier (LNA) integrated on a semiconductor die, where the LNA includes first and second differential pair transistors with an embedded inductor tail integrated on the semiconductor die. The embedded inductor tail may include: a first inductor with a first terminal capacitively-coupled to a gate terminal of the first differential pair transistor and a second terminal of the first inductor coupled to second, third, and fourth inductors. The second inductor may be coupled to a source terminal of the first differential pair transistor, the fourth inductor may be coupled to a source terminal of the second differential pair transistor, and the third inductor may be capacitively-coupled to a gate terminal of the second differential pair transistor and also to ground. The second inductor may be embedded within the first inductor.

Embodiments of the disclosure relate to a frequency selective low noise amplifier (LNA) circuit, which includes a transconductive LNA(s). In one aspect, filter circuitry is provided in a degeneration path of a transconductive LNA(s) to pass in-band frequencies and reject out-of-band frequencies by generating low impedance and high impedance at the in-band frequencies and the out-of-band frequencies, respectively. However, having the filter circuitry in the degeneration path may cause instability in the transconductive LNA. As such, a feedback path is coupled between an input node of the transconductive LNA(s) and the degeneration path to provide a feedback to improve stability of the transconductive LNA(s). In addition, the feedback can help improve impedance match in the frequency selective LNA circuit. As a result, the transconductive LNA(s) is able to achieve improved noise figure (NF) (e.g., below 1.5 dB), return loss, linearity, and stability, without compromising LNA gain.

A compensation circuit of a power amplifier includes a varactor, a voltage sensor and a control circuit. The varactor is coupled to an input terminal of the power amplifier. The voltage sensor is arranged for detecting an amplitude of an input signal of the power amplifier to generate a detecting result. The control circuit is coupled to the varactor and the voltage sensor, and is arranged for controlling a bias voltage of the varactor to adjust a capacitance of the varactor according to the detecting result.

A differential transceiver circuit coupled to a single antenna interface, the transceiver circuit comprising: a differential pair of signal paths, comprising a first signal path and a second signal path; differential amplifier, having an input arranged to receive a receive signal from the antenna interface; a differential transmitter arranged to generate a differential pair comprising a first transmit signal connected to the first signal path and a second transmit signal connected to the second signal path; a switching network arranged to divert the amplifier output on the second signal path to a signal ground node. The receive signal on one signal path is diverted to ground. The transmit signal corresponding to the other differential signal path is inserted so that the same transmit signal is present on both differential signal paths. When processed by differential downstream components with high common-mode rejection, the transmit signals cancel out.

An apparatus includes: first and second transistors, each of the first and second transistors includes a gate terminal, a source terminal, and a drain terminal; and a transformer including a primary winding and first and second secondary windings, the primary winding is coupled to a first input node configured to receive an input signal and a second input node configured to receive a potential, the first and second secondary windings are coupled to gate terminals of the first and second transistors and cross-coupled to source terminals of the first and second transistors.

Disclosed are apparatuses and methods to overcome technology limitations to achieve linearity and efficiency performance suitable for practical wireless communications systems. In an embodiment, an amplifier is provided that superimposes the transconductance from a common source amplifier with inductor degeneration with the transconductance from a common source amplifier without degeneration. In an embodiment, an amplifier is provided having a feedback-balun-transformer that provides electro-magnetic coupling between primary, secondary, and negative feedback degeneration inductors and a differential to single-ended conversion output.

An electronic device may include wireless circuitry with a processor, a transceiver circuit, a front-end module, and an antenna. The front-end module may include amplifier circuitry such as a low noise amplifier for amplifying received radio-frequency signals. The amplifier circuitry may include non-linearity suppression circuitry that suppresses or reduces non-linear behavior of components such as a core amplification transistor and a degeneration inductor within the amplifier circuitry. The non-linearity suppression circuitry may include an intermodulation distortion suppression circuit having an auxiliary amplification transistor. The non-linearity suppression circuitry may include a frequency-selective filter coupled to the degeneration inductor.