Techniques and apparatus for reducing sensitivity (e.g., less gain variation due to parasitic capacitance) in dynamic amplifiers. One example dynamic amplifier generally includes a pair of differential input transistors, a pair of cross-coupled switches coupled between the pair of differential input transistors and a pair of differential output nodes for the dynamic amplifier, a first pair of switches coupled between the pair of differential input transistors and the pair of differential output nodes, and a second pair of switches coupled between the pair of differential input transistors and the pair of differential output nodes.

An embodiment includes a track and hold amplifier device. A device may include an emitter follower transistor coupled to each of an input and an output. The device may also include a charging node coupled between the output and a voltage supply, wherein the charging node is also coupled to the input via the emitter follower transistor. Further, the device may include a cascode switch coupled to each of the input and the output. The cascode switch may be configured to cause the emitter follower transistor to operate in a conductive state and charge the charging node during a track mode. The cascode switch may also be configured to cause the emitter follower transistor to operate in a non-conductive state to isolate the charging node from the input during a hold mode. The cascode switch may include a MOS-HBT transistor combination operating in class AB mode.

Methods, systems, and devices for differential amplifier schemes for sensing memory cells are described. In one example, a memory apparatus may include a differential amplifier having a first input node configured to be coupled with a memory cell and having an output node configured to be coupled with a sense component. In some examples, the memory apparatus may also include a capacitor having a first node coupled with the first input node, and a first switching component configured to selectively couple a second node of the capacitor with the output node. The differential amplifier may configured such that a current at the output node is proportional to a difference between a voltage at the first input node of the differential amplifier and a voltage at the second input node of the differential amplifier.

A voltage regulator and a power supply are provided. The voltage regulator includes an operational amplifier and an offset voltage control module. The operational amplifier includes an input terminal and an output terminal, and is configured to generate an output voltage to be output from the output terminal based on a reference voltage received from the input terminal. The offset voltage control module includes one stage of regulation branch or more stages of regulation branches connected in parallel, and is configured to control an offset voltage of the operational amplifier based on selection of the regulation branch to regulate the output voltage. Since sine each stage of regulation branch in the offset voltage control module is based on a transistor structure, as compared with the voltage dividing resistor in the related art, the transistor has lower power consumption, and thus power consumption of the voltage regulator is lowered.

The disclosure provides an amplifier. The amplifier includes a first transistor that receives a first input and generates a first load current. A first output node is coupled to a power supply through a first load resistor. The first load resistor receives the first load current. A first capacitor network is coupled to the first output node and draws a first capacitive current from the first output node. A first current buffer is coupled between the first output node and the first transistor. A current through the first current buffer is a summation of the first load current and the first capacitive current.

An apparatus, such as a coherent optical receiver, includes a TIA, the TIA including a cascode circuit having a cascode node. A first tunable element is connected to tunably shunt the cascode node to vary a voltage gain of the TIA, e.g., up to a first amount. Implementations of the TIA further include another tunable element connected to vary a load of the cascode circuit to vary the voltage gain, e.g., up to a second amount. A current steering circuit may be provided to vary the voltage gain up to a third amount, each of the amounts being only a fraction of a target voltage gain variation of the TIA.

A multiplying digital-to-analog conversion circuit for use in an analog-to-digital converter is disclosed. In one aspect, the circuit comprises an input block including a capacitor and arranged for switchably connecting a first terminal of the capacitor to an input voltage signal during a first phase and to a fixed reference voltage during a second phase, a sub-analog-to-digital conversion circuit connected to a second terminal of the capacitor and arranged for quantizing a voltage on the capacitor during the second phase, a sub-digital-to-analog conversion circuit that receives the quantized version of the voltage and outputs an analog voltage derived from the quantized version, a feedback block including an amplifier connected to the second terminal of the capacitor and producing, at an amplifier output during a third phase, a residue signal corresponding to a combination of the input voltage signal and the analog voltage, and a feedback circuit.

The disclosure provides an amplifier. The amplifier includes a first transistor that receives a first input and generates a first load current. A first output node is coupled to a power supply through a first load resistor. The first load resistor receives the first load current. A first capacitor network is coupled to the first output node and draws a first capacitive current from the first output node. A first current buffer is coupled between the first output node and the first transistor. A current through the first current buffer is a summation of the first load current and the first capacitive current.

Amplifier configuration for load-line enhancement is described herein. In some implementations, an apparatus includes an amplifier. The amplifier includes at least one plus transistor stack, at least one minus transistor stack, and at least one inductor. The at least one plus transistor stack is coupled to a plus amplifier node and a plus input node. The at least one minus transistor stack is coupled to a minus amplifier node and a minus input node. The at least one inductor is coupled between the plus amplifier node and the minus amplifier node, with the at least one inductor including an inter-inductor node. The amplifier also includes a minus power switch coupled between the minus amplifier node and one or more supply voltages and an inductor power switch coupled between the inter-inductor node and at least one supply voltage.

A dynamic amplification circuit includes a first drive circuit (310) generates a first driving voltage according to a first control signal and a first driving current; a second drive circuit (320) generates a first driving signal according to the first and a second driving voltage; a third drive circuit (330) generates a second control signal according to the first control signal and the first driving signal; and a dynamic amplifier DA (340) includes a first branch (101) including a first capacitor and a second branch (102) including a second capacitor which are connected by a first resistor (150) and a second resistor (160), an operation state of the DA (340) is controlled through the first and second control signals, a duration of the DA (340) in an amplification phase is proportional to a product of a resistance value of the first resistor and a capacitance value of the first capacitor.