A dynamic common reference input (CMRI) signal may be provided to an operational amplifier, or op-amp, in an amplifier system to reduce the common mode ripple of the fully-differential op-amp, while adding little or no noise in the amplifier system. The dynamic CMRI signal may be controlled such that a common-mode component of two amplifier input nodes of the operational amplifier is made approximately independent of two input signals received at two system input nodes of the amplifier system. An amplifier system with the dynamic CMRI may be used in class-D amplifiers, such as amplifiers for audio systems that generate output for headphones or speakers.

A receiver includes a signal receiving part suitable for outputting a signal corresponding to a reception signal that is received through an input terminal, and controlling a DC voltage of a signal to be outputted, according to an offset signal, an amplifying part suitable for amplifying and outputting an output of the signal receiving part, and a feedback control part suitable for controlling the offset signal according to an output of the amplifying part.

A semiconductor device is provided that includes a first chip that generates a single signal by connecting a first signal line and a second signal line, to which differential signals are respectively provided, and outputs the single signal to a third signal line. The first chip is driven by a first power supply voltage. The semiconductor device also includes a second chip comprising an analog-to-digital converter (ADC) that receives the single signal through the third signal line, compares the single signal with a reference voltage, and outputs a digital signal based on the comparison. The semiconductor device also includes a controller that monitors the digital signal and adjusts the reference voltage to be approximately equivalent to the first power supply voltage.

A class-D amplifier includes a loop filter, a pulse-width modulation (PWM) circuit, an output circuit, and a common-mode control circuit. The loop filter receives an input signal of the class-D amplifier to generate a filtered signal. The PWM circuit converts a non-PWM signal into a PWM signal, wherein the non-PWM signal is derived from at least the filtered signal. The output circuit generates an output signal of the class-D amplifier according to the PWM signal. The common-mode control circuit monitors a common-mode level of the output signal to generate a common-mode control signal for PWM common-mode control.

A semiconductor device is provided that includes a first chip that generates a single signal by connecting a first signal line and a second signal line, to which differential signals are respectively provided, and outputs the single signal to a third signal line. The first chip is driven by a first power supply voltage. The semiconductor device also includes a second chip comprising an analog-to-digital converter (ADC) that receives the single signal through the third signal line, compares the single signal with a reference voltage, and outputs a digital signal based on the comparison. The semiconductor device also includes a controller that monitors the digital signal and adjusts the reference voltage to be approximately equivalent to the first power supply voltage.

A multi-modality intraoperative neurophysiological monitoring (IONM) system includes at least one amplifier integrated with a programmable switch matrix module configured to have up to 32 patient connected electrode inputs that are multiplexed to up to 24 amplifier channels. In some scenarios, a capacitor is positioned in series with electrode inputs of the at least one amplifier, such that the capacitor eliminates DC offset voltages from the electrode inputs while allowing neural AC signals to pass through to the at least one amplifier. In some scenarios, the switch matrix module includes a digital control loop configured to automatically eliminate offset voltage potential in patient connected electrodes. The switch matrix module further includes a field programmable gate array (FPGA) configured to automatically reset a plurality of control lines of one or more multiplexers of the switch matrix module.

A differential amplifier circuit is provided. The circuit includes a PWM modulator for generating a PWM signal representative of a difference between the first and the second staircase-like reference signals and the digital input signal, a DM-IDAC for receiving the PWM signal and providing a first and second differential mode current, a CM-IDAC for receiving the PWM signal and providing a common mode current, first and second loop integrators, and first and second comparators; each loop integrator comprising virtual ground node terminal for receiving the differential mode current, the common mode current, and a feedback signal from an output stage of the differential amplifier circuit via a feedback loop, and integrator output terminal for providing loop integrator output signal proportional to an integral of the signals received at the virtual ground node terminal, the comparators receiving the loop integrator output signal, and triangular reference signal.