In circuitry to capture differences between magnitudes of first and second comparator input signals in capture operations defined by a clock signal, first and second nodes are connectable to a tail node receiving a cock-signal-independent bias current along first and second paths. During each capture operation, switching circuitry controls connections between the tall node and the first and second nodes based on the input signals to divide the bias current between the first and second paths depending on the input signal magnitude difference. The switching circuitry comprises first and second transistors arranged such that conductivity of connections between the tail node and the first and second nodes Is controlled by the magnitudes of the input signals, and third and fourth non-clocked transistors controlled by a clock-signal independent gate bias signal.

Provided are a transmitting device connected to a receiving device via a channel and the receiving device connected to the transmitting device via a channel. The transmitting device connected to a receiving device includes: a transmitter connected to the channel via an output node and configured to transmit, via the channel, a transmission signal to the receiving device, the transmitter having a transmission impedance associated therewith that is variable; and a monitoring device configured to detect a channel impedance of the channel and a receiving impedance of the receiving device by monitoring a voltage level of the output node, the monitoring device configured to set the transmission impedance based on the channel impedance and the receiving impedance.

A traveling wave amplifier includes two input-side lines, two output-side lines, and amplification cells. The amplification cells each include a first input terminal, a second input terminal, a first transistor including a base connected to the first input terminal and a collector connected to one output-side line, a second transistor including a base connected to the second input terminal and a collector connected to the other output-side line, a current source connected to an emitter of each of the two transistors, a first series circuit connected between the collector of the second transistor and the base of the first transistor and including a capacitor and a resistor, and a second series of circuit connected between the collector of the first transistor and the base of the second transistor and including a capacitor and a resistor.

Provided are a transmitting device connected to a receiving device via a channel and the receiving device connected to the transmitting device via a channel. The transmitting device connected to a receiving device includes: a transmitter connected to the channel via an output node and configured to transmit, via the channel, a transmission signal to the receiving device, the transmitter having a transmission impedance associated therewith that is variable; and a monitoring device configured to detect a channel impedance of the channel and a receiving impedance of the receiving device by monitoring a voltage level of the output node, the monitoring device configured to set the transmission impedance based on the channel impedance and the receiving impedance.

A drive circuit for a serial communications system is provided. The drive circuit may include a mode controller, a pre-drive circuit, and a main drive circuit. The main drive circuit includes multiple mode control switches and at least one pair of differential switches. The mode controller is configured to: generate a mode control signal, and transmit the mode control signal to the main drive circuit. The pre-drive circuit is configured to: convert a differential digital signal into a differential control signal, and transmit the differential control signal to the main drive circuit. The main drive circuit controls on/off states of the multiple mode control switches according to the mode control signal, and works in corresponding working modes. The drive circuit controls the states of the mode control switches in the main drive circuit, so that the main drive circuit works in different working modes.

A current feed-back instrumentation amplifier (CFIA) comprises a differential pair with degeneration for amplifying small differential voltages in the presence of large common-mode voltages. The CFIA includes input and feedback transconductors and a chopping modulator circuit that continuously swaps tail current sources between the transconductors. This tail current swapping reduces the contribution to the CFIA's gain error caused by random mismatch between the tail currents of the input and feedback transconductors. The modulator circuit operates on a clock cycle to periodically swap the tail current sources. As a result, even if the tail currents are mismatched, on average the tail currents (transconductor gains) will approximately equal out, and the contribution of the tail current difference to the gain error is canceled out.

A current feed-back instrumentation amplifier (CFIA) comprises a differential pair with degeneration for amplifying small differential voltages in the presence of large common-mode voltages. The CFIA includes input and feedback transconductors and a trimming circuit that trims the back-bias voltages of the transistors in each transconductor. The trimming circuit includes a plurality of selectable resistors disposed in the signal path of the tail current in each transconductor. Each of the plurality of selectable resistors has a switch coupled to it. When a switch is closed, only the resistors up to the respective switch are in the signal path of the bulk-to-source voltage of the differentially paired transistors. The resistor trimming circuit reduces the mismatch between transconductances of the respective differential pair transistors, in turn reducing mismatch of the overall transconductances of the transconductors, and thereby reducing the CFIA's gain error.

In circuitry to capture differences between magnitudes of first and second comparator input signals in capture operations defined by a clock signal, first and second nodes are connectable to a tail node receiving a clock-signal-independent bias current along first and second paths. During each capture operation, switching circuitry controls connections between the tail node and the first and second nodes based on the input signals to divide the bias current between the first and second paths depending on the input signal magnitude difference. The switching circuitry comprises first and second transistors arranged such that conductivity of connections between the tail node and the first and second nodes is controlled by the magnitudes of the input signals, and third and fourth non-clocked transistors controlled by a clock-signal independent gate bias signal.

A current feed-back instrumentation amplifier (CFIA) comprises a differential pair with degeneration for amplifying small differential voltages in the presence of large common-mode voltages. The CFIA includes input and feedback transconductors and a trimming circuit that trims the back-bias voltages of the transistors in each transconductor. The trimming circuit includes a plurality of selectable resistors disposed in the signal path of the tail current in each transconductor. Each of the plurality of selectable resistors has a switch coupled to it. When a switch is closed, only the resistors up to the respective switch are in the signal path of the bulk-to-source voltage of the differentially paired transistors. The resistor trimming circuit reduces the mismatch between transconductances of the respective differential pair transistors, in turn reducing mismatch of the overall transconductances of the transconductors, and thereby reducing the CFIA's gain error.

A variable gain amplifier capable of stabilizing an average output potential of a differential output signal, improving power efficiency over a wide range of an amplitude of the differential input signal, and suppressing deterioration of a distortion rate is provided. The variable gain amplifier includes an amplifying circuit configured to amplify a differential input signal with a gain according to a gain control signal, and a current control circuit. The amplifying circuit has a first current source supplying a source current. The current control circuit adjusts a magnitude of the source current of the first current source according to a magnitude of the gain control signal.