Patent classifications
H03F2203/45466
PROGRAMMABLE IMPEDANCE NETWORK IN AN AMPLIFIER
The disclosure provides an amplifier. The amplifier includes a first transistor that receives a first input. A second transistor receives a second input. A plurality of impedance networks is coupled between the first transistor and the second transistor. At least one impedance network of the plurality of impedance networks includes a first impedance path and a second impedance path. The first impedance path is activated during single ended operation, and the second impedance path is activated during differential operation.
Detection device, sensor, electronic apparatus, and moving object
A detection device includes a driving circuit which drives a physical quantity transducer, a detection circuit which detects a desired signal, a power-supply terminal into which a power-supply voltage is input, a regulator circuit which performs a voltage adjustment of stepping down the power-supply voltage from the power-supply terminal, and supplies a regulated power-supply voltage obtained by the voltage adjustment to the driving circuit and the detection circuit as an operating power-supply voltage, and a buffer circuit which is supplied with the power-supply voltage, receives a drive signal from the driving circuit, and outputs an amplified drive signal in which an amplitude of the drive signal increases to the physical quantity transducer.
Programmable impedance network in an amplifier
The disclosure provides an amplifier. The amplifier includes a first transistor that receives a first input. A second transistor receives a second input. A plurality of impedance networks is coupled between the first transistor and the second transistor. At least one impedance network of the plurality of impedance networks includes a first impedance path and a second impedance path. The first impedance path is activated during single ended operation, and the second impedance path is activated during differential operation.
SEMICONDUCTOR APPARATUS AND RECEIVER THEREOF
A semiconductor apparatus includes a receiver configured to generate an output signal by amplifying an input signal received through a channel, and compensate distortion of the input signal based on a control signal preset according to a voltage level of the input signal, and an internal circuit configured to operate in response to the output signal.
Amplifier circuit with improved accuracy
An amplifier circuit with improved accuracy is provided that comprises a cascade of amplifier stages, a control line for controlling the amplifier stages, a feedback circuit having an input port for receiving a reference signal, and a feedback loop connecting the feedback circuit to the control line. Via the feedback circuit and the feedback loop, the large signal behavior of the amplifier stage is accurately fixed. As a result, the small signal gain of the amplifier stages has an improved accuracy as well.
ESA phase shifter topology
A phase shifter component is described. Inputs are arranged to selectively receive an inphase component of an in-phase (I) signal or an outphase I signal 180 out of phase with the inphase I signal, and to selectively receive an inphase component of a quadrature-phase (Q) signal or an outphase Q signal 180 out of phase with the inphase Q signal. A first gain portion includes only two transistor elements arranged to amplify the received outphase or inphase I signal. A second gain portion includes only two transistor elements arranged to amplify the received outphase or inphase Q signal. The first and second gain portions are configured to control the gain of the received outphase or inphase I signal and the received outphase or inphase Q signal, respectively, to provide a composite output signal with a desired phase shift between 0 and 360.