In some embodiments, a differential input stage comprises a first n-type metal oxide semiconductor transistor (NMOS) pair coupled to a first input and a second input, a second NMOS pair coupled to the first input, a first output node, the second input, and a second output node, a first diode coupled to the first NMOS pair and the first output node, a second diode coupled to the first NMOS pair and the second output node, and a cascaded current source coupled to the first NMOS pair and the second NMOS pair.

An amplifier system with high gain, compact size, and extended bandwidth is disclosed. The amplifier system includes one or more inputs configured to receive one or more input signals and a pre-driver configured to receive the one or more input signals. The pre-driver may comprise source connected FETs which create a virtual ground and may include inductors which cancel or counter parasitic capacitance of the FETs. The pre-driver amplifies the one or more input signals to create one or more pre-amplified signals, which are provided to a voltage divider network configured to reduce a DC bias voltage of the one or more pre-amplified signals, while maintaining a wide bandwidth range. An amplifier receives and amplifies the output of the voltage divider network to create amplified signals. The amplifier may comprise mirrored FET pairs in a common source configuration and a common gate arrangement.

An example apparatus includes: buffer circuitry including: a first transistor having a first terminal, a second terminal, and a control terminal; and a second transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the second transistor coupled to the first terminal of the first transistor, the control terminal of the second transistor coupled to the control terminal of the first transistor; output stage circuitry including: gate biasing circuitry having a terminal; a third transistor having a first terminal and a control terminal, the control terminal of the third transistor coupled to the second terminal of the second transistor and the terminal of the gate biasing circuitry; current mirror circuitry having an input and an output, the input of the current mirror circuitry coupled to the second terminal of the first transistor.

A transconductance amplifier that generates an output voltage by amplifying a difference between an input voltage and a reference voltage, includes: a differential amplifier circuit including an input differential pair configured to receive the input voltage and the reference voltage and operate according to a tail current, and an output circuit provided as an active load of the input differential pair to generate the output voltage; and a current control circuit configured to control the tail current, wherein the current control circuit is configured to increase the tail current when a current supply condition is satisfied, and the current supply condition is that the input voltage falls below a first threshold voltage which is equal to or lower than the reference voltage, or that the input voltage exceeds a second threshold voltage which is equal to or higher than the reference voltage.

A differential input stage includes first and second input transistors with current flow paths are coupled between a tail transistor current flow path and first and second nodes, respectively. An output stage includes first and second output transistors having current flow paths between a supply line and first and second output nodes, respectively, coupled to the first and second nodes. First and second common-mode control transistors have current flow paths jointly coupled to a ground current flow path of a common-mode tail transistor. The first common-mode control transistor has a control terminal resistively coupled to the first and second output nodes. A bias duplicate transistor has a current flow path arranged in a bias current flow line between the supply line and ground. The bias duplicate transistor is coupled in a 1:N current mirror arrangement with the tail transistor in the differential input stage.